89 lines
4.5 KiB
VHDL
89 lines
4.5 KiB
VHDL
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-- Execute custom RISC-V instructions structure:
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----------------------------------------------------------------------------------------
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--| 7bits | 5bits | 6bits | 1bit | 1bit | 1bit | 5bit | 7bit |
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--| Funct | rs2 | rs1 | xd | xs1 | xs2 | rd | opcode |
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--|31 25|24 20|19 15| 14 | 13 | 12 |11 7|6 0|
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----------------------------------------------------------------------------------------
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--ROCC_INSTRUCTION_RS1_RS2(x, rs1, rs2, funct) variables avaliable for baremetalC is rs1,rs2-register address and funct-function
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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----------------------RoCC Interface Entity---------------------------
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entity RoCC_Interface is
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port(
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clk : in std_logic;
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rst : in std_logic;
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cmd_valid : in std_logic; --From Core
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Cmd_inst_funct : in std_logic_vector(6 downto 0); --From Core
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Cmd_inst_opcode : in std_logic_vector(6 downto 0); --From Core
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Cmd_inst_rd : in std_logic_vector(4 downto 0); --From Core
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Cmd_inst_rs1 : in std_logic_vector(4 downto 0); --From Core
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Cmd_inst_rs2 : in std_logic_vector(4 downto 0); --From Core
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Cmd_inst_xd : in std_logic; --From Core
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Cmd_inst_xs1 : in std_logic; --From Core
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Cmd_inst_xs2 : in std_logic; --From Core
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Cmd_rs1 : in std_logic_vector(63 downto 0); --From Core
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Cmd_rs2 : in std_logic_vector(63 downto 0); --From Core
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Data_trans_from_DMA : in std_logic_vector(4 downto 0); --From DMA
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Cmd_busy : out std_logic; --To Core
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Cmd_ready : out std_logic; --To Core --always one
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Funct_to_DMA : out std_logic_vector(6 downto 0); --To DMA
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Address_to_DMA : out std_logic_vector(6 downto 0); --To DMA
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Size_to_DMA : out std_logic_vector(4 downto 0) --To DMA
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);
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end entity;
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----------------------Rocc Interface Behaviour------------------------
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architecture Noc_Interface_Arch of Noc_Interface is
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Signal Cmd_rs1_sig : std_logic_vector(63 downto 0);
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signal Cmd_rs1_sig : std_logic_vector(63 downto 0);
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Signal Cmd_inst_funct_sig : std_logic_vector(6 downto 0);
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Signal cmd_valid_sig : std_logic;
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--signal Sent_packet : std_logic_vector(4 downto 0);
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--signal packet_length : std_logic_vector(4 downto 0);
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begin
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process(clk, rst)
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begin
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if rst = '0' then
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Cmd_busy <= '0';
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Cmd_ready <= '1'; --To Core --always one
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cmd_valid_sig <= '0';
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Funct_to_DMA <= (others => '0');
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Address_to_DMA <= (others => '0');
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Size_to_DMA <= (others => '0');
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Cmd_rs1_sig <= (others => '0');
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Cmd_rs1_sig <= (others => '0');
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Cmd_inst_funct_sig <= (others => '0');
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elsif rising_edge(clk) then
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--------------------Reading from RoCC--------------------------------
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if (cmd_valid = '1') then
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Cmd_rs1_sig <= Cmd_rs1;
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Cmd_rs2_sig <= Cmd_rs2; --size 4 downto 0 [5bits]
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Cmd_inst_funct_sig <= Cmd_inst_funct;
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cmd_valid_sig <= '1';
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end if;
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--------------------Send to the DMA--------------------------------
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if(cmd_valid_sig = '1' and Cmd_rs2_sig(4 downto 0) > Data_trans_from_DMA) then
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Funct_to_DMA <= Cmd_inst_funct_sig;
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Address_to_DMA <= Cmd_rs1_sig(6 downto 0);
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Size_to_DMA <= Cmd_rs2_sig(4 downto 0);
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else
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cmd_valid_sig <= '0';
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Cmd_rs1_sig <= (others => '0');
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Cmd_rs1_sig <= (others => '0');
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Cmd_inst_funct_sig <= (others => '0');
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end if;
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end if;
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end process;
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end architecture;
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