65 lines
2.3 KiB
VHDL
65 lines
2.3 KiB
VHDL
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-------------------------------------------------------------------------------
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-- Title : Credit counter for one vc in an output port (physcial channel)
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-- Project : Modular, heterogenous 3D NoC
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-------------------------------------------------------------------------------
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-- File : credit_count_single.vhd
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-- Author : Lennart Bamberg <lennart@t440s>
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-- Company :
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-- Created : 2018-11-19
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-- Last update: 2018-11-28
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-- Platform :
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-- Standard : VHDL'93/02
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-------------------------------------------------------------------------------
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-- Description: Uses increment and vc_write_tx to determine if another flit can
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-- be written to the VC in the input prot of teh adjacent router.
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-------------------------------------------------------------------------------
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-- Copyright (c) 2018
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-------------------------------------------------------------------------------
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-- Revisions :
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-- Date Version Author Description
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-- 2018-11-19 1.0 lennart Created
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.NOC_3D_PACKAGE.all;
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entity credit_count_single is
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generic (
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-- buffer space in output vc at the other router
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vc_depth_out : positive := 4
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);
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port(
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clk, rst : in std_logic;
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incr_rx : in std_logic;
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vc_write_tx : in std_logic;
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credit_avail : out std_logic);
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end entity credit_count_single;
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architecture rtl of credit_count_single is
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signal count_val : unsigned(bit_width(vc_depth_out+1)-1 downto 0);
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signal credit_avail_int : std_logic;
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begin -- architecture rtl
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process(clk, rst)
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begin
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if rst = RST_LVL then
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count_val <= to_unsigned(vc_depth_out, count_val'length);
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elsif rising_edge(clk) then
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if incr_rx = '1' and vc_write_tx = '0' then
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count_val <= count_val +1;
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elsif incr_rx = '0' and vc_write_tx = '1' then
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count_val <= count_val - 1;
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end if;
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end if;
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end process;
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credit_avail_int <= '1' when count_val > 0 else '0';
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-- potential infinite loop if output is not pipelined!
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credit_avail <= credit_avail_int or incr_rx;
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-- to avoid infinite loop ...
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-- credit_avail <= credit_avail_int;
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end architecture rtl;
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