81 lines
2.9 KiB
VHDL
81 lines
2.9 KiB
VHDL
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-------------------------------------------------------------------------------
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-- Title : Sequential packet counter
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-- Project : Modular, heterogenous 3D NoC
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-------------------------------------------------------------------------------
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-- File : seq_packet_counter.vhd
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-- Author : Lennart Bamberg <bamberg@office.item.uni-bremen.de>
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-- Company : University of Bremen
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-- Created : 2018-11-28
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-- Last update: 2018-11-28
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-- Platform :
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-- Standard : VHDL'93/02
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-------------------------------------------------------------------------------
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-- Description: When a new packet is assigend, the coutner is set to the packet
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-- length. Whenever a flit is transfered, the counter is decr.
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-------------------------------------------------------------------------------
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-- Copyright (c) 2018 University of Bremen
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-------------------------------------------------------------------------------
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-- Revisions :
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-- Date Version Author Description
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-- 2018-11-28 1.0 bamberg Created
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_misc.all;
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use work.NOC_3D_PACKAGE.all;
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entity seq_packet_counter is
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generic (
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header_incl_in_packet_length : boolean := true);
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port(
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clk, rst : in std_logic;
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allocated : in std_logic;
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packet_len : in std_logic_vector(packet_len_width-1 downto 0);
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enr_vc : in std_logic;
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flit_count : out unsigned(packet_len_width-1 downto 0));
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end entity seq_packet_counter;
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architecture rtl of seq_packet_counter is
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signal flit_count_nxt, flit_count_load, flit_count_int
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: unsigned(packet_len_width-1 downto 0);
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begin
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-----------------------------------------------------------------------------
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-- Flip Flop Counter --------------------------------------------------------
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-----------------------------------------------------------------------------
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process(clk, rst)
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begin
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if rst = RST_LVL then
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flit_count_int <= (others => '0');
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elsif clk'event and clk = '1' then
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if (allocated or enr_vc) = '1' then -- flip flop enable
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flit_count_int <= flit_count_nxt;
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end if;
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end if;
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end process;
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-----------------------------------------------------------------------------
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-- Combinatorial ------------------------------------------------------------
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-----------------------------------------------------------------------------
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flit_count_load <= unsigned(packet_len) when header_incl_in_packet_length
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else (unsigned(packet_len)+1);
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process(allocated, enr_vc, flit_count_int, flit_count_load)
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begin
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if allocated = '1' and enr_vc = '0' then
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flit_count_nxt <= flit_count_load;
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elsif allocated = '0' and enr_vc = '1' then
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flit_count_nxt <= flit_count_int-1;
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else
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flit_count_nxt <= (others => '-');
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end if;
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end process;
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flit_count <= flit_count_int;
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end architecture;
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