diff --git a/DMA_CONTROLLER.vhd b/DMA_CONTROLLER.vhd index da28408..9d55915 100644 --- a/DMA_CONTROLLER.vhd +++ b/DMA_CONTROLLER.vhd @@ -4,29 +4,38 @@ use ieee.numeric_std.all; ----------------------DMA Controller Entity--------------------------- entity DMA_Controller is + -- constant DATA_SIZE : integer := 7; -- Define constant for vector size for data of 8 bits + -- constant ADDRESS_SIZE : integer := 6; -- Define constant for vector size for address 7 bits + -- constant ID_SIZE : integer := 4; -- Define constant for vector size for size of Id's 5 bits + generic ( + DATA_SIZE : integer := 7; -- Define constant for vector size for data of 8 bits + ADDRESS_SIZE : integer := 6; -- Define constant for vector size for address 7 bits + ID_SIZE : integer := 4 -- Define constant for vector size for size of Id's 5 bits + ); port( clk : in std_logic; rst : in std_logic; - rx_packet_length_noc_to_DMA : in std_logic_vector(4 downto 0); --To DMA From Noc - Receive_valid_to_DMA_from_Noc : in std_logic; --To DMA From Noc - Sent_Ack_to_DMA_from_Noc : in std_logic_vector(4 downto 0);--------To DMA From Noc - Funct_core_to_DMA : in std_logic_vector(6 downto 0); --To DMA From Core - Address_core_to_DMA : in std_logic_vector(6 downto 0); --To DMA From Core - Size_core_to_DMA : in std_logic_vector(4 downto 0); --To DMA From Core - Address_bus_From_DMA : out std_logic_vector(7 downto 0); --From DMA To RAM - Read_write_Enable_From_DMA : out std_logic_vector(1 downto 0); --From DMA To RAM - Sent_valid_from_DMA_to_NoC : out std_logic; --From DMA To NoC - tx_packet_length_noc_From_DMA : out std_logic_vector(4 downto 0); --From DMA To NoC - Data_trans_from_DMA_to_core : out std_logic_vector(4 downto 0) --From DMA To Core + rx_packet_length_noc_to_DMA : in std_logic_vector(ID_SIZE downto 0); --To DMA From Noc + Receive_valid_to_DMA_from_Noc : in std_logic; --To DMA From Noc + Sent_Ack_to_DMA_from_Noc : in std_logic_vector(ID_SIZE downto 0);--------To DMA From Noc + Funct_core_to_DMA : in std_logic_vector(ADDRESS_SIZE downto 0); --To DMA From Core + Address_core_to_DMA : in std_logic_vector(ADDRESS_SIZE downto 0); --To DMA From Core + Size_core_to_DMA : in std_logic_vector(ID_SIZE downto 0); --To DMA From Core + Address_bus_From_DMA : out std_logic_vector(ADDRESS_SIZE downto 0); --From DMA To RAM + Read_Enable_From_DMA : out std_logic; --From DMA To RAM + Write_Enable_From_DMA : out std_logic; --From DMA To RAM + Sent_valid_from_DMA_to_NoC : out std_logic; --From DMA To NoC + tx_packet_length_noc_From_DMA : out std_logic_vector(ID_SIZE downto 0); --From DMA To NoC + Data_trans_from_DMA_to_core : out std_logic_vector(ID_SIZE downto 0) --From DMA To Core ); end entity; ----------------------DMA Controller Behaviour------------------------ architecture DMA_Controller_Arch of DMA_Controller is - Signal Count_from_NoC : std_logic_vector(4 downto 0); - Signal Count_to_NoC : std_logic_vector(4 downto 0); - Signal Address_to_RAM : std_logic_vector(6 downto 0); + Signal Count_from_NoC : std_logic_vector(ID_SIZE downto 0); + Signal Count_to_NoC : std_logic_vector(ID_SIZE downto 0); + Signal Address_to_RAM : std_logic_vector(ADDRESS_SIZE downto 0); begin @@ -34,8 +43,9 @@ begin begin if rst = '0' then Sent_valid_from_DMA_to_NoC <= '0'; + Read_Enable_From_DMA <= '0'; + Write_Enable_From_DMA <= '0'; Address_bus_From_DMA <= (others => '0'); - Read_write_Enable_From_DMA <= (others => '0'); tx_packet_length_noc_From_DMA <= (others => '0'); Data_trans_from_DMA_to_core <= (others => '0'); Count_from_NoC <= (others => '0'); @@ -46,45 +56,70 @@ begin elsif rising_edge(clk) then ----------------------Writing to RAM from NOC------------------------ - if Funct_core_to_DMA = "111 1111" then --- x"7f" is just randomly choosen value <[need to find an funct]> - if Count_from_NoC < Size_core_to_DMA then --comparing rx_packet_length_noc_to_DMA = Size_core_to_DMA - if Count_from_NoC = "00000" then + if Funct_core_to_DMA = std_logic_vector(to_unsigned(15, 7)) then --- x"0f" 15 Its arbitarly choosen from RoCC_Interface + if unsigned(Count_to_NoC) < (unsigned(Size_core_to_DMA)) then --+10 will reproduce same valid signal comparing rx_packet_length_noc_to_DMA = Size_core_to_DMA + if Count_to_NoC = "00000" then ---count_from_Noc but not working in the wave simulation Address_to_RAM <= Address_core_to_DMA; - end if; - if Receive_valid_to_DMA_from_Noc = '1' then + Count_to_NoC <= std_logic_vector(unsigned(Count_to_NoC) + 1); + --Write_Enable_From_DMA <= '1'; --Write Enable + --end if; + elsif Receive_valid_to_DMA_from_Noc = '1' then Address_bus_From_DMA <= Address_to_RAM; - Read_write_Enable_From_DMA <= "01"; --Write Enable - Data_trans_from_DMA_to_core <= Count_from_NoC; - Address_to_RAM <= Address_to_RAM + 1; - Count_from_NoC <= Count_from_NoC + 1; - + --report "Write_Enable_From_DMA is 1 from Line 68"; + Write_Enable_From_DMA <= '1'; --Write Enable ----<<<>>> + Read_Enable_From_DMA <= '0'; --'0' + Data_trans_from_DMA_to_core <= Count_to_NoC ;-- std_logic_vector(unsigned(Count_to_NoC) - 1) + Address_to_RAM <= std_logic_vector(unsigned(Address_to_RAM) + 1); + Count_to_NoC <= std_logic_vector(unsigned(Count_to_NoC) + 1); + else + ----report "Write_Enable_From_DMA is 0 from Line 75"; + Write_Enable_From_DMA <= '0'; --Write Enable ----<<<>>> + Read_Enable_From_DMA <= '0'; --'0' end if; + + else + ----report "Write_Enable_From_DMA is 0 from Line 75"; + Write_Enable_From_DMA <= '0'; --Write Enable ----<<<>>> + Read_Enable_From_DMA <= '0'; --'0' end if; - else - Count_from_NoC <= (others => '0'); - Read_write_Enable_From_DMA <= (others => '0'); - - end if; + -- else + -- Count_from_NoC <= (others => '0'); + -- Read_Enable_From_DMA <= '0'; + -- Write_Enable_From_DMA <= 'Z';--'0'; + -- Sent_valid_from_DMA_to_NoC <= '0'; + -- end if; ----------------------Reading from RAM to NOC------------------------ - if Funct_core_to_DMA = "111 0000" then --- x"70" is just randomly choosen value <[need to find an funct]> - if Count_to_NoC < Size_core_to_DMA then --Sent_Ack_to_DMA_from_Noc could be used instead of the count to Noc + elsif Funct_core_to_DMA = std_logic_vector(to_unsigned(127, 7)) then --- x"7f" 127 Its arbitarly choosen from RoCC_Interface + if unsigned(Count_to_NoC) < unsigned(Size_core_to_DMA) then --Sent_Ack_to_DMA_from_Noc could be used instead of the count to Noc if Count_to_NoC = "00000" then Address_to_RAM <= Address_core_to_DMA; tx_packet_length_noc_From_DMA <= Size_core_to_DMA; --giving the size to the header of the NoC flit + Count_to_NoC <= std_logic_vector(unsigned(Count_to_NoC) + 1); + ---Sent_valid_from_DMA_to_NoC <= '1'; + else + Address_bus_From_DMA <= Address_to_RAM; + Write_Enable_From_DMA <= '0'; + Read_Enable_From_DMA <= '1'; --Read Enable + Data_trans_from_DMA_to_core <= Sent_Ack_to_DMA_from_Noc; + Address_to_RAM <= std_logic_vector(unsigned(Address_to_RAM) + 1); + Count_to_NoC <= std_logic_vector(unsigned(Count_to_NoC) + 1); + Sent_valid_from_DMA_to_NoC <= '1'; end if; - Address_bus_From_DMA <= Address_to_RAM; - Read_write_Enable_From_DMA <= "10"; --Write Enable - Data_trans_from_DMA_to_core <= Sent_Ack_to_DMA_from_Noc; - Address_to_RAM <= Address_to_RAM + 1; - Count_to_NoC <= Count_to_NoC + 1; + elsif unsigned(Count_to_NoC) < (unsigned(Size_core_to_DMA)+2) then + Count_to_NoC <= std_logic_vector(unsigned(Count_to_NoC) + 1); Sent_valid_from_DMA_to_NoC <= '1'; - + else + Read_Enable_From_DMA <= '0'; + Write_Enable_From_DMA <= '0'; + Sent_valid_from_DMA_to_NoC <= '0'; end if; else - Count_from_NoC <= (others => '0'); - Read_write_Enable_From_DMA <= (others => '0'); - + Count_to_NoC <= (others => '0'); + Read_Enable_From_DMA <= '0'; + --report "Write_Enable_From_DMA is 0 from Line 111"; + Write_Enable_From_DMA <= '0'; + Sent_valid_from_DMA_to_NoC <= '0'; end if; end if; end process; diff --git a/FULL_DMA.vhd b/FULL_DMA.vhd index dfed775..c8c7f8b 100644 --- a/FULL_DMA.vhd +++ b/FULL_DMA.vhd @@ -4,30 +4,40 @@ use ieee.numeric_std.all; ----------------------Full DMA Entity--------------------------- entity Full_DMA is + -- constant DATA_SIZE : integer := 7; -- Define constant for vector size for data of 8 bits + -- constant INST_SIZE : integer := 6; -- Define constant for vector size for inst of 6 bits + -- constant LENGTH : integer := 4; -- Define constant for vector size for size of Id's 5 bits + -- constant PACKET : integer := 31; -- Define constant for vector size for size of packet 32 bits + -- constant REG_SIZE : integer := 63; -- Define constant for vector size for size of Reg 64 bits generic ( - SOURCE_ID_NEW : std_logic_vector(5 downto 0) := "000000"; -- Default source ID should be changed - DEST_ID_NEW : std_logic_vector(5 downto 0) := "000001" -- Default destination ID should be changed + DATA_SIZE : integer := 7; -- Define constant for vector size for data of 8 bits + INST_SIZE : integer := 6; -- Define constant for vector size for inst of 6 bits + LENGTH : integer := 4; -- Define constant for vector size for size of Id's 5 bits + PACKET : integer := 31; -- Define constant for vector size for size of packet 32 bits + REG_SIZE : integer := 63; -- Define constant for vector size for size of Reg 64 bits + SOURCE_ID_NEW : std_logic_vector(5 downto 0) := "000000"; -- Default source ID should be changed + DEST_ID_NEW : std_logic_vector(5 downto 0) := "000001" -- Default destination ID should be changed ); port( clk : in std_logic; rst : in std_logic; - local_noc_rx : in std_logic_vector(31 downto 0);--- --From Noc + local_noc_rx : in std_logic_vector(PACKET downto 0);--- --From Noc local_vc_write_tx_noc : in std_logic; ---_vector(192-1 downto 0);--From NoC cmd_valid : in std_logic; --From Core - Cmd_inst_funct : in std_logic_vector(6 downto 0); --From Core - Cmd_inst_opcode : in std_logic_vector(6 downto 0); --From Core - Cmd_inst_rd : in std_logic_vector(4 downto 0); --From Core - Cmd_inst_rs1 : in std_logic_vector(4 downto 0); --From Core - Cmd_inst_rs2 : in std_logic_vector(4 downto 0); --From Core + Cmd_inst_funct : in std_logic_vector(INST_SIZE downto 0); --From Core + Cmd_inst_opcode : in std_logic_vector(INST_SIZE downto 0); --From Core + Cmd_inst_rd : in std_logic_vector(LENGTH downto 0); --From Core + Cmd_inst_rs1 : in std_logic_vector(LENGTH downto 0); --From Core + Cmd_inst_rs2 : in std_logic_vector(LENGTH downto 0); --From Core Cmd_inst_xd : in std_logic; --From Core Cmd_inst_xs1 : in std_logic; --From Core Cmd_inst_xs2 : in std_logic; --From Core - Cmd_rs1 : in std_logic_vector(63 downto 0); --From Core - Cmd_rs2 : in std_logic_vector(63 downto 0); --From Core + Cmd_rs1 : in std_logic_vector(REG_SIZE downto 0); --From Core + Cmd_rs2 : in std_logic_vector(REG_SIZE downto 0); --From Core Cmd_busy : out std_logic; --To Core Cmd_ready : out std_logic; --To Core --always one - local_noc_tx : out std_logic_vector(31 downto 0);--- --To NoC - local_vc_write_rx_noc : out std_logic ---_vector(192-1 downto 0);--To NoC + local_noc_tx : out std_logic_vector(PACKET downto 0);--- --To NoC + local_vc_write_rx_noc : out std_logic ---_vector(192-1 downto 0); --To NoC ); end entity; @@ -39,104 +49,115 @@ architecture Full_DMA_Arch of Full_DMA is port( clk : in std_logic; rst : in std_logic; - Address_bus : in std_logic_vector(7 downto 0); --From DMA - Read_write_Enable : in std_logic_vector(1 downto 0); --From DMA - Data_bus_in : in std_logic_vector(7 downto 0); --From Noc - Data_bus_out : out std_logic_vector(7 downto 0) --From Noc + Address_bus : in std_logic_vector(INST_SIZE downto 0); --From DMA + Read_Enable : in std_logic; --From DMA + Write_Enable : in std_logic; --From DMA + Data_bus_in : in std_logic_vector(DATA_SIZE downto 0); --From Noc + Data_bus_out : out std_logic_vector(DATA_SIZE downto 0) --From Noc ); end component; component Noc_Interface is generic ( - SOURCE_ID : std_logic_vector(5 downto 0) := "000000"; -- Default source ID should be changed - DEST_ID : std_logic_vector(5 downto 0) := "000001" -- Default destination ID should be changed + SOURCE_ID : std_logic_vector(5 downto 0) := "000000"; -- Default source ID should be changed + DEST_ID : std_logic_vector(5 downto 0) := "000001" -- Default destination ID should be changed ); port( clk : in std_logic; rst : in std_logic; - Sent_valid_from_DMA : in std_logic; --From DMA - Data_bus_noc_in : in std_logic_vector(7 downto 0); --From RAM - tx_packet_length_noc : in std_logic_vector(4 downto 0); --From DMA - local_noc_rx : in std_logic_vector(31 downto 0);--- --From Noc - local_vc_write_tx_noc: in std_logic; ---_vector(192-1 downto 0);--From NoC - rx_packet_length_noc : out std_logic_vector(4 downto 0); --To DMA - local_noc_tx : out std_logic_vector(31 downto 0);--- --To NoC - local_vc_write_rx_noc: out std_logic; ---_vector(192-1 downto 0);--To NoC - Receive_valid_to_DMA : out std_logic; --To DMA - Sent_Ack_to_DMA : out std_logic_vector(4 downto 0);-----------To DMA - Data_bus_noc_out : out std_logic_vector(7 downto 0) --To RAM + Sent_valid_from_DMA : in std_logic; --From DMA + Data_bus_noc_in : in std_logic_vector(DATA_SIZE downto 0); --From RAM + tx_packet_length_noc : in std_logic_vector(LENGTH downto 0); --From DMA + local_noc_rx : in std_logic_vector(PACKET downto 0);--- --From Noc + local_vc_write_tx_noc: in std_logic; ---_vector(192-1 downto 0); --From NoC + rx_packet_length_noc : out std_logic_vector(LENGTH downto 0); --To DMA + local_noc_tx : out std_logic_vector(PACKET downto 0);--- --To NoC + local_vc_write_rx_noc: out std_logic; ---_vector(192-1 downto 0); --To NoC + Receive_valid_to_DMA : out std_logic; --To DMA + Sent_Ack_to_DMA : out std_logic_vector(LENGTH downto 0);---------To DMA + Data_bus_noc_out : out std_logic_vector(DATA_SIZE downto 0) --To RAM ); end component; component RoCC_Interface is port( clk : in std_logic; rst : in std_logic; - cmd_valid : in std_logic; --From Core - Cmd_inst_funct : in std_logic_vector(6 downto 0); --From Core - Cmd_inst_opcode : in std_logic_vector(6 downto 0); --From Core - Cmd_inst_rd : in std_logic_vector(4 downto 0); --From Core - Cmd_inst_rs1 : in std_logic_vector(4 downto 0); --From Core - Cmd_inst_rs2 : in std_logic_vector(4 downto 0); --From Core - Cmd_inst_xd : in std_logic; --From Core - Cmd_inst_xs1 : in std_logic; --From Core - Cmd_inst_xs2 : in std_logic; --From Core - Cmd_rs1 : in std_logic_vector(63 downto 0); --From Core - Cmd_rs2 : in std_logic_vector(63 downto 0); --From Core - Data_trans_from_DMA : in std_logic_vector(4 downto 0); --From DMA - Cmd_busy : out std_logic; --To Core - Cmd_ready : out std_logic; --To Core --always one - Funct_to_DMA : out std_logic_vector(6 downto 0); --To DMA - Address_to_DMA : out std_logic_vector(6 downto 0); --To DMA - Size_to_DMA : out std_logic_vector(4 downto 0) --To DMA + cmd_valid : in std_logic; --From Core + Cmd_inst_funct : in std_logic_vector(INST_SIZE downto 0); --From Core + Cmd_inst_opcode : in std_logic_vector(INST_SIZE downto 0); --From Core + Cmd_inst_rd : in std_logic_vector(LENGTH downto 0); --From Core + Cmd_inst_rs1 : in std_logic_vector(LENGTH downto 0); --From Core + Cmd_inst_rs2 : in std_logic_vector(LENGTH downto 0); --From Core + Cmd_inst_xd : in std_logic; --From Core + Cmd_inst_xs1 : in std_logic; --From Core + Cmd_inst_xs2 : in std_logic; --From Core + Cmd_rs1 : in std_logic_vector(REG_SIZE downto 0); --From Core + Cmd_rs2 : in std_logic_vector(REG_SIZE downto 0); --From Core + Data_trans_from_DMA : in std_logic_vector(LENGTH downto 0); --From DMA + Cmd_busy : out std_logic; --To Core + Cmd_ready : out std_logic; --To Core --always one + Funct_to_DMA : out std_logic_vector(INST_SIZE downto 0); --To DMA + Address_to_DMA : out std_logic_vector(INST_SIZE downto 0); --To DMA + Size_to_DMA : out std_logic_vector(LENGTH downto 0) --To DMA ); end component; component DMA_Controller is port( clk : in std_logic; rst : in std_logic; - rx_packet_length_noc_to_DMA : in std_logic_vector(4 downto 0); --To DMA From Noc - Receive_valid_to_DMA_from_Noc : in std_logic; --To DMA From Noc - Sent_Ack_to_DMA_from_Noc : in std_logic_vector(4 downto 0);--------To DMA From Noc - Funct_core_to_DMA : in std_logic_vector(6 downto 0); --To DMA From Core - Address_core_to_DMA : in std_logic_vector(6 downto 0); --To DMA From Core - Size_core_to_DMA : in std_logic_vector(4 downto 0); --To DMA From Core - Address_bus_From_DMA : out std_logic_vector(7 downto 0); --From DMA To RAM - Read_write_Enable_From_DMA : out std_logic_vector(1 downto 0); --From DMA To RAM - Sent_valid_from_DMA_to_NoC : out std_logic; --From DMA To NoC - tx_packet_length_noc_From_DMA : out std_logic_vector(4 downto 0); --From DMA To NoC - Data_trans_from_DMA_to_core : out std_logic_vector(4 downto 0) --From DMA To Core + rx_packet_length_noc_to_DMA : in std_logic_vector(LENGTH downto 0); --To DMA From Noc + Receive_valid_to_DMA_from_Noc : in std_logic; --To DMA From Noc + Sent_Ack_to_DMA_from_Noc : in std_logic_vector(LENGTH downto 0);--------To DMA From Noc + Funct_core_to_DMA : in std_logic_vector(INST_SIZE downto 0); --To DMA From Core + Address_core_to_DMA : in std_logic_vector(INST_SIZE downto 0); --To DMA From Core + Size_core_to_DMA : in std_logic_vector(LENGTH downto 0); --To DMA From Core + Address_bus_From_DMA : out std_logic_vector(INST_SIZE downto 0); --From DMA To RAM + Read_Enable_From_DMA : out std_logic; --From DMA To RAM + Write_Enable_From_DMA : out std_logic; --From DMA To RAM + Sent_valid_from_DMA_to_NoC : out std_logic; --From DMA To NoC + tx_packet_length_noc_From_DMA : out std_logic_vector(LENGTH downto 0); --From DMA To NoC + Data_trans_from_DMA_to_core : out std_logic_vector(LENGTH downto 0) --From DMA To Core ); end component; - signal Address_bus_sig : std_logic_vector(7 downto 0); - signal Read_write_Enable_sig : std_logic_vector(1 downto 0); - signal Data_bus_in_sig : std_logic_vector(7 downto 0); - signal Data_bus_out_sig : std_logic_vector(7 downto 0); + + signal Address_bus_sig : std_logic_vector(INST_SIZE downto 0); + signal Read_Enable_sig : std_logic; + signal Write_Enable_sig : std_logic; + -- signal Read_write_Enable_sig : std_logic_vector(1 downto 0); + signal Data_bus_in_sig : std_logic_vector(DATA_SIZE downto 0); + signal Data_bus_out_sig : std_logic_vector(DATA_SIZE downto 0); + signal Sent_valid_from_DMA_sig : std_logic; - signal Data_bus_noc_in_sig : std_logic_vector(7 downto 0); - signal tx_packet_length_noc_sig : std_logic_vector(4 downto 0); - signal rx_packet_length_noc_sig : std_logic_vector(4 downto 0); - signal local_noc_tx_sig : std_logic_vector(31 downto 0); - signal local_vc_write_rx_noc_sig : std_logic; + --signal Data_bus_noc_in_sig : std_logic_vector(DATA_SIZE downto 0); + signal tx_packet_length_noc_sig : std_logic_vector(LENGTH downto 0); + signal rx_packet_length_noc_sig : std_logic_vector(LENGTH downto 0); + --signal local_noc_tx_sig : std_logic_vector(PACKET downto 0); + --signal local_vc_write_rx_noc_sig : std_logic; signal Receive_valid_to_DMA_sig : std_logic; - signal Sent_Ack_to_DMA_sig : std_logic_vector(4 downto 0); - signal Data_bus_noc_out_sig : std_logic_vector(7 downto 0); + signal Sent_Ack_to_DMA_sig : std_logic_vector(LENGTH downto 0); + --signal Data_bus_noc_out_sig : std_logic_vector(DATA_SIZE downto 0); + + signal Data_trans_from_DMA_sig : std_logic_vector(LENGTH downto 0); + signal Funct_to_DMA_sig : std_logic_vector(INST_SIZE downto 0); + signal Address_to_DMA_sig : std_logic_vector(INST_SIZE downto 0); + signal Size_to_DMA_sig : std_logic_vector(LENGTH downto 0); + + --signal rx_packet_length_noc_to_DMA_sig : std_logic_vector(LENGTH downto 0); + -- signal Receive_valid_to_DMA_from_Noc_sig : std_logic; + --signal Sent_Ack_to_DMA_from_Noc_sig : std_logic_vector(LENGTH downto 0); + --signal Funct_core_to_DMA_sig : std_logic_vector(INST_SIZE downto 0); + --signal Address_core_to_DMA_sig : std_logic_vector(INST_SIZE downto 0); + --Signal Size_core_to_DMA_sig : std_logic_vector(LENGTH downto 0); + --signal Address_bus_From_DMA_sig : std_logic_vector(DATA_SIZE downto 0); + -- signal Read_write_Enable_From_DMA_sig : std_logic_vector(1 downto 0); + --signal Sent_valid_from_DMA_to_NoC_sig : std_logic; + --signal tx_packet_length_noc_From_DMA_sig : std_logic_vector(LENGTH downto 0); + --signal Data_trans_from_DMA_to_core_sig : std_logic_vector(LENGTH downto 0); + + + - signal Data_trans_from_DMA_sig : std_logic_vector(4 downto 0); - signal Funct_to_DMA_sig : std_logic_vector(6 downto 0); - signal Address_to_DMA_sig : std_logic_vector(6 downto 0); - signal Size_to_DMA_sig : std_logic_vector(4 downto 0); - signal rx_packet_length_noc_to_DMA_sig : std_logic_vector(4 downto 0); - signal Receive_valid_to_DMA_from_Noc_sig : std_logic; - signal Sent_Ack_to_DMA_from_Noc_sig : std_logic_vector(4 downto 0); - signal Funct_core_to_DMA_sig : std_logic_vector(6 downto 0); - signal Address_core_to_DMA_sig : std_logic_vector(6 downto 0); - Signal Size_core_to_DMA_sig : std_logic_vector(4 downto 0); - signal Address_bus_From_DMA_sig : std_logic_vector(7 downto 0); - signal Read_write_Enable_From_DMA_sig : std_logic_vector(1 downto 0); - signal Sent_valid_from_DMA_to_NoC_sig : std_logic; - signal tx_packet_length_noc_From_DMA_sig : std_logic_vector(4 downto 0); - signal Data_trans_from_DMA_to_core_sig : std_logic_vector(4 downto 0); begin -- Single_Port_RAM mapping Single_Port_RAM_inst : Single_Port_RAM @@ -144,7 +165,8 @@ architecture Full_DMA_Arch of Full_DMA is clk => clk, rst => rst, Address_bus => Address_bus_sig, - Read_write_Enable => Read_write_Enable_sig, + Read_Enable => Read_Enable_sig, + Write_Enable => Write_Enable_sig, Data_bus_in => Data_bus_in_sig, -- Assuming data input comes from NoC Data_bus_out => Data_bus_out_sig ); @@ -160,7 +182,7 @@ architecture Full_DMA_Arch of Full_DMA is clk => clk, rst => rst, Sent_valid_from_DMA => Sent_valid_from_DMA_sig, - Data_bus_noc_in => Data_bus_in_sig, + Data_bus_noc_in => Data_bus_out_sig, tx_packet_length_noc => tx_packet_length_noc_sig, local_noc_rx => local_noc_rx, --- local_vc_write_tx_noc=> local_vc_write_tx_noc, --- @@ -169,7 +191,7 @@ architecture Full_DMA_Arch of Full_DMA is local_vc_write_rx_noc=> local_vc_write_rx_noc, --- Receive_valid_to_DMA => Receive_valid_to_DMA_sig, Sent_Ack_to_DMA => Sent_Ack_to_DMA_sig, - Data_bus_noc_out => Data_bus_out_sig + Data_bus_noc_out => Data_bus_in_sig ); -- RoCC_Interface mapping @@ -178,19 +200,19 @@ architecture Full_DMA_Arch of Full_DMA is clk => clk, rst => rst, cmd_valid => cmd_valid, --- - Cmd_inst_funct => Cmd_inst_funct, --- - Cmd_inst_opcode => Cmd_inst_opcode, --- - Cmd_inst_rd => Cmd_inst_rd, --- - Cmd_inst_rs1 => Cmd_inst_rs1, --- - Cmd_inst_rs2 => Cmd_inst_rs2, --- - Cmd_inst_xd => Cmd_inst_xd, --- - Cmd_inst_xs1 => Cmd_inst_xs1, --- - Cmd_inst_xs2 => Cmd_inst_xs2, --- - Cmd_rs1 => Cmd_rs1, --- - Cmd_rs2 => Cmd_rs2, --- + Cmd_inst_funct => Cmd_inst_funct, --- + Cmd_inst_opcode => Cmd_inst_opcode, --- + Cmd_inst_rd => Cmd_inst_rd, --- + Cmd_inst_rs1 => Cmd_inst_rs1, --- + Cmd_inst_rs2 => Cmd_inst_rs2, --- + Cmd_inst_xd => Cmd_inst_xd, --- + Cmd_inst_xs1 => Cmd_inst_xs1, --- + Cmd_inst_xs2 => Cmd_inst_xs2, --- + Cmd_rs1 => Cmd_rs1, --- + Cmd_rs2 => Cmd_rs2, --- Data_trans_from_DMA => Data_trans_from_DMA_sig, - Cmd_busy => Cmd_busy, --- - Cmd_ready => Cmd_ready, --- + Cmd_busy => Cmd_busy, --- + Cmd_ready => Cmd_ready, --- Funct_to_DMA => Funct_to_DMA_sig, Address_to_DMA => Address_to_DMA_sig, Size_to_DMA => Size_to_DMA_sig @@ -201,17 +223,56 @@ architecture Full_DMA_Arch of Full_DMA is port map( clk => clk, rst => rst, - rx_packet_length_noc_to_DMA => rx_packet_length_noc_to_DMA_sig, - Receive_valid_to_DMA_from_Noc => Receive_valid_to_DMA_from_Noc_sig, - Sent_Ack_to_DMA_from_Noc => Sent_Ack_to_DMA_from_Noc_sig, - Funct_core_to_DMA => Funct_core_to_DMA_sig, - Address_core_to_DMA => Address_core_to_DMA_sig, - Size_core_to_DMA => Size_core_to_DMA_sig, - Address_bus_From_DMA => Address_bus_From_DMA_sig, - Read_write_Enable_From_DMA => Read_write_Enable_From_DMA_sig, - Sent_valid_from_DMA_to_NoC => Sent_valid_from_DMA_to_NoC_sig, - tx_packet_length_noc_From_DMA => tx_packet_length_noc_From_DMA_sig, - Data_trans_from_DMA_to_core => Data_trans_from_DMA_to_core_sig + rx_packet_length_noc_to_DMA => rx_packet_length_noc_sig, + Receive_valid_to_DMA_from_Noc => Receive_valid_to_DMA_sig, + Sent_Ack_to_DMA_from_Noc => Sent_Ack_to_DMA_sig, + Funct_core_to_DMA => Funct_to_DMA_sig, + Address_core_to_DMA => Address_to_DMA_sig, + Size_core_to_DMA => Size_to_DMA_sig, + Address_bus_From_DMA => Address_bus_sig, + Read_Enable_From_DMA => Read_Enable_sig, + Write_Enable_From_DMA => Write_Enable_sig, + Sent_valid_from_DMA_to_NoC => Sent_valid_from_DMA_sig, + tx_packet_length_noc_From_DMA => tx_packet_length_noc_sig, + Data_trans_from_DMA_to_core => Data_trans_from_DMA_sig ); - ----mapping need to be done yet------------- \ No newline at end of file + +end architecture; + + ----mapping need to be done yet------------- + + + + -- signal Address_bus_sig : std_logic_vector(DATA_SIZE downto 0); +-- -- signal Read_write_Enable_sig : std_logic_vector(1 downto 0); +-- signal Data_bus_in_sig : std_logic_vector(DATA_SIZE downto 0); +-- signal Data_bus_out_sig : std_logic_vector(DATA_SIZE downto 0); + +-- signal Sent_valid_from_DMA_sig : std_logic; +-- signal Data_bus_noc_in_sig : std_logic_vector(DATA_SIZE downto 0); +-- signal tx_packet_length_noc_sig : std_logic_vector(LENGTH downto 0); +-- signal rx_packet_length_noc_sig : std_logic_vector(LENGTH downto 0); +-- signal local_noc_tx_sig : std_logic_vector(PACKET downto 0); +-- signal local_vc_write_rx_noc_sig : std_logic; +-- signal Receive_valid_to_DMA_sig : std_logic; +-- signal Sent_Ack_to_DMA_sig : std_logic_vector(LENGTH downto 0); +-- signal Data_bus_noc_out_sig : std_logic_vector(DATA_SIZE downto 0); + +-- signal Data_trans_from_DMA_sig : std_logic_vector(LENGTH downto 0); +-- signal Funct_to_DMA_sig : std_logic_vector(INST_SIZE downto 0); +-- signal Address_to_DMA_sig : std_logic_vector(INST_SIZE downto 0); +-- signal Size_to_DMA_sig : std_logic_vector(LENGTH downto 0); + +-- signal rx_packet_length_noc_to_DMA_sig : std_logic_vector(LENGTH downto 0); +-- signal Receive_valid_to_DMA_from_Noc_sig : std_logic; +-- signal Sent_Ack_to_DMA_from_Noc_sig : std_logic_vector(LENGTH downto 0); +-- signal Funct_core_to_DMA_sig : std_logic_vector(INST_SIZE downto 0); +-- signal Address_core_to_DMA_sig : std_logic_vector(INST_SIZE downto 0); +-- Signal Size_core_to_DMA_sig : std_logic_vector(LENGTH downto 0); +-- signal Address_bus_From_DMA_sig : std_logic_vector(DATA_SIZE downto 0); +-- -- signal Read_write_Enable_From_DMA_sig : std_logic_vector(1 downto 0); +-- signal Sent_valid_from_DMA_to_NoC_sig : std_logic; +-- signal tx_packet_length_noc_From_DMA_sig : std_logic_vector(LENGTH downto 0); +-- signal Data_trans_from_DMA_to_core_sig : std_logic_vector(LENGTH downto 0); + diff --git a/FULL_DMA_tb.vhd b/FULL_DMA_tb.vhd new file mode 100644 index 0000000..ce3c329 --- /dev/null +++ b/FULL_DMA_tb.vhd @@ -0,0 +1,170 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +---vsim -gui work.fulldmatb +entity fulldmaTB is +end entity; + +architecture fulldmaTB_arch of fulldmaTB is + constant DATA_SIZE : integer := 7; -- Define constant for vector size for data of 8 bits + constant INST_SIZE : integer := 6; -- Define constant for vector size for inst of 6 bits + constant LENGTH : integer := 4; -- Define constant for vector size for size of Id's 5 bits + constant PACKET : integer := 31; -- Define constant for vector size for size of packet 32 bits + constant REG_SIZE : integer := 63; -- Define constant for vector size for size of Reg 64 bits + component Full_DMA is + generic ( + DATA_SIZE : integer := 7; -- Define constant for vector size for data of 8 bits + INST_SIZE : integer := 6; -- Define constant for vector size for inst of 6 bits + LENGTH : integer := 4; -- Define constant for vector size for size of Id's 5 bits + PACKET : integer := 31; -- Define constant for vector size for size of packet 32 bits + REG_SIZE : integer := 63; -- Define constant for vector size for size of Reg 64 bits + SOURCE_ID_NEW : std_logic_vector(5 downto 0) := "000000"; -- Default source ID should be changed + DEST_ID_NEW : std_logic_vector(5 downto 0) := "000001" -- Default destination ID should be changed + ); + port( + clk : in std_logic; + rst : in std_logic; + local_noc_rx : in std_logic_vector(PACKET downto 0);--- --From Noc + local_vc_write_tx_noc : in std_logic; ---_vector(192-1 downto 0);--From NoC + cmd_valid : in std_logic; --From Core + Cmd_inst_funct : in std_logic_vector(INST_SIZE downto 0); --From Core + Cmd_inst_opcode : in std_logic_vector(INST_SIZE downto 0); --From Core + Cmd_inst_rd : in std_logic_vector(LENGTH downto 0); --From Core + Cmd_inst_rs1 : in std_logic_vector(LENGTH downto 0); --From Core + Cmd_inst_rs2 : in std_logic_vector(LENGTH downto 0); --From Core + Cmd_inst_xd : in std_logic; --From Core + Cmd_inst_xs1 : in std_logic; --From Core + Cmd_inst_xs2 : in std_logic; --From Core + Cmd_rs1 : in std_logic_vector(REG_SIZE downto 0); --From Core + Cmd_rs2 : in std_logic_vector(REG_SIZE downto 0); --From Core + Cmd_busy : out std_logic; --To Core + Cmd_ready : out std_logic; --To Core --always one + local_noc_tx : out std_logic_vector(PACKET downto 0);--- --To NoC + local_vc_write_rx_noc : out std_logic ---_vector(192-1 downto 0); --To NoC + + ); + end component; + + signal clk_tb : std_logic; + signal rst_tb : std_logic; + signal local_noc_rx1, local_noc_rx2 : std_logic_vector(PACKET downto 0); + signal local_vc_write_tx_noc1 : std_logic; + signal cmd_valid,local_vc_write_tx_noc2 : std_logic; + signal Cmd_inst_funct1,Cmd_inst_funct2 : std_logic_vector(INST_SIZE downto 0); + signal Cmd_inst_opcode : std_logic_vector(INST_SIZE downto 0); + signal Cmd_inst_rd : std_logic_vector(LENGTH downto 0); + signal Cmd_inst_rs1 : std_logic_vector(LENGTH downto 0); + signal Cmd_inst_rs2 : std_logic_vector(LENGTH downto 0); + signal Cmd_inst_xd : std_logic; + signal Cmd_inst_xs1 : std_logic; + signal Cmd_inst_xs2 : std_logic; + signal Cmd_rs1_1, Cmd_rs1_2 : std_logic_vector(REG_SIZE downto 0); + signal Cmd_rs2_1, Cmd_rs2_2 : std_logic_vector(REG_SIZE downto 0); + signal Cmd_busy : std_logic; + signal Cmd_ready : std_logic; + signal local_noc_tx1, local_noc_tx2 : std_logic_vector(PACKET downto 0); + signal local_vc_write_rx_noc : std_logic; + +begin + -- Component instantiation with a label + fulldma_inst1 : Full_DMA + generic map ( + SOURCE_ID_NEW => "000001", -- Set source ID + DEST_ID_NEW => "000000" -- Set destination ID + ) + port map ( + clk => clk_tb, + rst => rst_tb, + local_noc_rx => local_noc_rx1, + local_vc_write_tx_noc => local_vc_write_tx_noc1, + cmd_valid => cmd_valid, + Cmd_inst_funct => Cmd_inst_funct1, + Cmd_inst_opcode => Cmd_inst_opcode, + Cmd_inst_rd => Cmd_inst_rd, + Cmd_inst_rs1 => Cmd_inst_rs1, + Cmd_inst_rs2 => Cmd_inst_rs2, + Cmd_inst_xd => Cmd_inst_xd, + Cmd_inst_xs1 => Cmd_inst_xs1, + Cmd_inst_xs2 => Cmd_inst_xs2, + Cmd_rs1 => Cmd_rs1_1, + Cmd_rs2 => Cmd_rs2_1, + Cmd_busy => Cmd_busy, + Cmd_ready => Cmd_ready, + local_noc_tx => local_noc_tx1, + local_vc_write_rx_noc => local_vc_write_rx_noc + ); + -- Component instantiation with a label + fulldma_inst2 : Full_DMA + generic map ( + SOURCE_ID_NEW => "000000", -- Set source ID + DEST_ID_NEW => "000001" -- Set destination ID + ) + port map ( + clk => clk_tb, + rst => rst_tb, + local_noc_rx => local_noc_rx2, + local_vc_write_tx_noc => local_vc_write_tx_noc2, + cmd_valid => cmd_valid, + Cmd_inst_funct => Cmd_inst_funct2, + Cmd_inst_opcode => Cmd_inst_opcode, + Cmd_inst_rd => Cmd_inst_rd, + Cmd_inst_rs1 => Cmd_inst_rs1, + Cmd_inst_rs2 => Cmd_inst_rs2, + Cmd_inst_xd => Cmd_inst_xd, + Cmd_inst_xs1 => Cmd_inst_xs1, + Cmd_inst_xs2 => Cmd_inst_xs2, + Cmd_rs1 => Cmd_rs1_2, + Cmd_rs2 => Cmd_rs2_2, + Cmd_busy => Cmd_busy, + Cmd_ready => Cmd_ready, + local_noc_tx => local_noc_tx2, + local_vc_write_rx_noc => local_vc_write_rx_noc + ); + + -- Clock generation process + clk_process: process + begin + clk_tb <= '0'; wait for 5 ns; + clk_tb <= '1'; wait for 5 ns; + end process; + -----------------------NoC connection has to be changed-------------------- + local_noc_rx1 <= local_noc_tx2; + local_noc_rx2 <= local_noc_tx1; + + + -- Simulation process to assign values to CtrlCommand + simproc: process + begin + local_vc_write_tx_noc2 <= '0'; + cmd_valid <= '0'; + rst_tb <= '0'; + wait for 10 ns; + rst_tb <= '1'; + wait for 40 ns; + + + + Cmd_inst_funct2 <= "0011110"; --#define DMA_WRITE_TO_RAM 30 /// 0X1E + Cmd_inst_funct1 <= "0011111"; --#define DMA_READ_FROM_RAM 31 /// 0X1F + + Cmd_rs1_1 <= std_logic_vector(to_unsigned(0, 57)) & "0000010"; --7 bit address & 57 bit zeros + Cmd_rs1_2 <= std_logic_vector(to_unsigned(0, 57)) & "0001000"; --7 bit address & 57 bit zeros + + Cmd_rs2_1 <= std_logic_vector(to_unsigned(0, 59)) & "00100"; --5 bit size & 59 bit zeros + Cmd_rs2_2 <= std_logic_vector(to_unsigned(0, 59)) & "00100"; --5 bit size & 59 bit zeros + + wait for 20 ns; + cmd_valid <= '1'; + wait for 40 ns; + cmd_valid <= '0'; + local_vc_write_tx_noc2 <= '1'; + wait for 80 ns; + local_vc_write_tx_noc2 <= '0'; + + + wait for 1000 ns; + + + -- wait for 1000 ns ; + end process; +end architecture; diff --git a/NoC_INTERFACE.vhd b/NoC_INTERFACE.vhd index 932d430..d2a6c8d 100644 --- a/NoC_INTERFACE.vhd +++ b/NoC_INTERFACE.vhd @@ -11,33 +11,43 @@ use ieee.numeric_std.all; ----------------------NoC Interface Entity--------------------------- entity Noc_Interface is + -- constant DATA_SIZE : integer := 7; -- Define constant for vector size for data of 8 bits + -- constant LENGTH : integer := 4; -- Define constant for vector size for size of Id's 5 bits + -- constant PACKET : integer := 11; -- Define constant for vector size for size of Id's 12 bits + -- constant REG_SIZE : integer := 31; -- Define constant for vector size for size of Reg 31 bits generic ( - SOURCE_ID : std_logic_vector(5 downto 0) := "000000"; -- Default source ID should be changed - DEST_ID : std_logic_vector(5 downto 0) := "000001" -- Default destination ID should be changed + DATA_SIZE : integer := 7; -- Define constant for vector size for data of 8 bits + LENGTH : integer := 4; -- Define constant for vector size for size of Id's 5 bits + PACKET : integer := 11; -- Define constant for vector size for size of Id's 12 bits + REG_SIZE : integer := 31; -- Define constant for vector size for size of Reg 31 bits + SOURCE_ID : std_logic_vector(5 downto 0) := "000000"; -- Default source ID should be changed + DEST_ID : std_logic_vector(5 downto 0) := "000001" -- Default destination ID should be changed ); port( clk : in std_logic; rst : in std_logic; Sent_valid_from_DMA : in std_logic; --From DMA - Data_bus_noc_in : in std_logic_vector(7 downto 0); --From RAM - tx_packet_length_noc : in std_logic_vector(4 downto 0); --From DMA - local_noc_rx : in std_logic_vector(31 downto 0);--- --From Noc + Data_bus_noc_in : in std_logic_vector(DATA_SIZE downto 0); --From RAM + tx_packet_length_noc : in std_logic_vector(LENGTH downto 0); --From DMA + local_noc_rx : in std_logic_vector(REG_SIZE downto 0);--- --From Noc local_vc_write_tx_noc: in std_logic; ---_vector(192-1 downto 0);--From NoC - rx_packet_length_noc : out std_logic_vector(4 downto 0); --To DMA - local_noc_tx : out std_logic_vector(31 downto 0);--- --To NoC + rx_packet_length_noc : out std_logic_vector(LENGTH downto 0); --To DMA + local_noc_tx : out std_logic_vector(REG_SIZE downto 0);--- --To NoC local_vc_write_rx_noc: out std_logic; ---_vector(192-1 downto 0);--To NoC Receive_valid_to_DMA : out std_logic; --To DMA - Sent_Ack_to_DMA : out std_logic_vector(4 downto 0);-----------To DMA - Data_bus_noc_out : out std_logic_vector(7 downto 0) --To RAM + Sent_Ack_to_DMA : out std_logic_vector(LENGTH downto 0);-----------To DMA + Data_bus_noc_out : out std_logic_vector(DATA_SIZE downto 0) --To RAM ); end entity; ----------------------NoC Interface Behaviour------------------------ architecture Noc_Interface_Arch of Noc_Interface is - Signal packet_id : std_logic_vector(11 downto 0); - signal count : std_logic_vector(4 downto 0); - signal Sent_packet : std_logic_vector(4 downto 0); + Signal packet_id : std_logic_vector(PACKET downto 0); + signal count : std_logic_vector(LENGTH downto 0); + signal Sent_packet : std_logic_vector(LENGTH downto 0); + signal packet_len : std_logic_vector(LENGTH downto 0); + --signal packet_length : std_logic_vector(4 downto 0); @@ -47,28 +57,35 @@ begin if rst = '0' then rx_packet_length_noc <= (others => '0'); local_noc_tx <= (others => '0'); - local_vc_write_rx_noc <= (others => '0'); - Receive_valid_to_DMA <= (others => '0'); + local_vc_write_rx_noc <= '0'; + Receive_valid_to_DMA <= '0'; Sent_Ack_to_DMA <= (others => '0'); Data_bus_noc_out <= (others => '0'); count <= (others => '0'); Sent_packet <= (others => '0'); packet_id <= (others => '0'); + packet_len <= (others => '0'); elsif rising_edge(clk) then --------------------Reading from NoC-------------------------------- if (local_vc_write_tx_noc = '1') then - if (local_vc_write_tx_noc(31 downto 29) = "100") then - rx_packet_length_noc <= local_vc_write_tx_noc(4 downto 0 ); --packet length - count <= (others => '0'); --counter reset - packet_id <= local_vc_write_tx_noc(28 downto 17); --current packetid - elsif(count < local_vc_write_tx_noc(4 downto 0 )) then - Receive_valid_to_DMA <= '1'; --valid to DMA - count <= count + 1; --counter update - Data_bus_noc_out <= local_vc_write_tx_noc(7 downto 0 ); --NoC is given to RAM + if (local_noc_rx(31 downto 29) = "100") then + rx_packet_length_noc <= local_noc_rx(LENGTH downto 0 ); --packet length + packet_len <= local_noc_rx(LENGTH downto 0 ); --packet length + count <= (others => '0'); --counter reset + packet_id <= local_noc_rx(28 downto 17); --current packetid + Receive_valid_to_DMA <= '1'; + elsif(unsigned(count) <= unsigned(packet_len) and unsigned(packet_len) > 0) then + report "Receive_valid_to_DMA is 1 from Line 80"; + + Receive_valid_to_DMA <= '1'; --valid to DMA + count <= std_logic_vector(unsigned(count) + 1); --counter update + Data_bus_noc_out <= local_noc_rx(DATA_SIZE downto 0 ); --NoC is given to RAM else + report "Receive_valid_to_DMA is 0 from Line 86"; + packet_len <= (others=>'0'); Receive_valid_to_DMA <= '0'; Data_bus_noc_out <= (others=>'0'); count <= (others=>'0'); @@ -76,24 +93,24 @@ begin --------------------Writing to NoC---------------------------------- - elsif (Sent_valid_from_DMA = '1' and tx_packet_length_noc > 0) then + elsif ((Sent_valid_from_DMA = '1') and (to_integer(unsigned(tx_packet_length_noc)) >= 0)) then -- the valid from dma is one cycle behind if(Sent_packet = "00000") then - Sent_Ack_to_DMA <= Sent_packet + 1; --to DMA updated value - Sent_packet <= Sent_packet + 1; + --Sent_Ack_to_DMA <= std_logic_vector(unsigned(Sent_packet) + 1); --to DMA updated value + Sent_packet <= std_logic_vector(unsigned(Sent_packet) + 1); --updating packet id local_noc_tx <= "100" & packet_id & SOURCE_ID & DEST_ID & tx_packet_length_noc; local_vc_write_rx_noc <= '1'; else - Sent_Ack_to_DMA <= Sent_packet + 1; --to DMA updated value - Sent_packet <= Sent_packet + 1; - local_noc_tx <= (others => '0') & Data_bus_noc_in;; --24bit zeros in msb and 8 bit data + Sent_Ack_to_DMA <= Sent_packet;--std_logic_vector(unsigned(Sent_packet) + 1); --to DMA updated value + Sent_packet <= std_logic_vector(unsigned(Sent_packet) + 1); + local_noc_tx <= std_logic_vector(to_unsigned(0, 24)) & Data_bus_noc_in; --24bit zeros in msb and 8 bit data local_vc_write_rx_noc <= '1'; end if; else rx_packet_length_noc <= (others => '0'); local_noc_tx <= (others => '0'); - local_vc_write_rx_noc <= (others => '0'); - Receive_valid_to_DMA <= (others => '0'); + local_vc_write_rx_noc <= '0'; + Receive_valid_to_DMA <= '0'; Sent_Ack_to_DMA <= (others => '0'); Data_bus_noc_out <= (others => '0'); count <= (others => '0'); diff --git a/ROCC_INTERFACE.vhd b/ROCC_INTERFACE.vhd index c4100a0..4c128f5 100644 --- a/ROCC_INTERFACE.vhd +++ b/ROCC_INTERFACE.vhd @@ -11,35 +11,45 @@ use ieee.numeric_std.all; ----------------------RoCC Interface Entity--------------------------- entity RoCC_Interface is + -- constant INST_SIZE : integer := 6; -- Define constant for vector size for inst of 6 bits + -- constant LENGTH : integer := 4; -- Define constant for vector size for size of Id's 5 bits + -- constant PACKET : integer := 11; -- Define constant for vector size for size of Id's 12 bits + -- constant REG_SIZE : integer := 63; -- Define constant for vector size for size of Reg 63 bits + generic ( + INST_SIZE : integer := 6; -- Define constant for vector size for inst of 6 bits + LENGTH : integer := 4; -- Define constant for vector size for size of Id's 5 bits + PACKET : integer := 11; -- Define constant for vector size for size of Id's 12 bits + REG_SIZE : integer := 63 -- Define constant for vector size for size of Reg 63 bits + ); port( clk : in std_logic; rst : in std_logic; - cmd_valid : in std_logic; --From Core - Cmd_inst_funct : in std_logic_vector(6 downto 0); --From Core - Cmd_inst_opcode : in std_logic_vector(6 downto 0); --From Core - Cmd_inst_rd : in std_logic_vector(4 downto 0); --From Core - Cmd_inst_rs1 : in std_logic_vector(4 downto 0); --From Core - Cmd_inst_rs2 : in std_logic_vector(4 downto 0); --From Core - Cmd_inst_xd : in std_logic; --From Core - Cmd_inst_xs1 : in std_logic; --From Core - Cmd_inst_xs2 : in std_logic; --From Core - Cmd_rs1 : in std_logic_vector(63 downto 0); --From Core - Cmd_rs2 : in std_logic_vector(63 downto 0); --From Core - Data_trans_from_DMA : in std_logic_vector(4 downto 0); --From DMA - Cmd_busy : out std_logic; --To Core - Cmd_ready : out std_logic; --To Core --always one - Funct_to_DMA : out std_logic_vector(6 downto 0); --To DMA - Address_to_DMA : out std_logic_vector(6 downto 0); --To DMA - Size_to_DMA : out std_logic_vector(4 downto 0) --To DMA + cmd_valid : in std_logic; --From Core + Cmd_inst_funct : in std_logic_vector(INST_SIZE downto 0); --From Core + Cmd_inst_opcode : in std_logic_vector(INST_SIZE downto 0); --From Core + Cmd_inst_rd : in std_logic_vector(LENGTH downto 0); --From Core + Cmd_inst_rs1 : in std_logic_vector(LENGTH downto 0); --From Core + Cmd_inst_rs2 : in std_logic_vector(LENGTH downto 0); --From Core + Cmd_inst_xd : in std_logic; --From Core + Cmd_inst_xs1 : in std_logic; --From Core + Cmd_inst_xs2 : in std_logic; --From Core + Cmd_rs1 : in std_logic_vector(REG_SIZE downto 0); --From Core + Cmd_rs2 : in std_logic_vector(REG_SIZE downto 0); --From Core + Data_trans_from_DMA : in std_logic_vector(LENGTH downto 0); --From DMA + Cmd_busy : out std_logic; --To Core + Cmd_ready : out std_logic; --To Core --always one + Funct_to_DMA : out std_logic_vector(INST_SIZE downto 0); --To DMA + Address_to_DMA : out std_logic_vector(INST_SIZE downto 0); --To DMA + Size_to_DMA : out std_logic_vector(LENGTH downto 0) --To DMA ); end entity; ----------------------Rocc Interface Behaviour------------------------ -architecture Noc_Interface_Arch of Noc_Interface is - Signal Cmd_rs1_sig : std_logic_vector(63 downto 0); - signal Cmd_rs1_sig : std_logic_vector(63 downto 0); - Signal Cmd_inst_funct_sig : std_logic_vector(6 downto 0); +architecture RoCC_Interface_Arch of RoCC_Interface is + Signal Cmd_rs1_sig : std_logic_vector(REG_SIZE downto 0); + signal Cmd_rs2_sig : std_logic_vector(REG_SIZE downto 0); + Signal Cmd_inst_funct_sig : std_logic_vector(INST_SIZE downto 0); Signal cmd_valid_sig : std_logic; --signal Sent_packet : std_logic_vector(4 downto 0); --signal packet_length : std_logic_vector(4 downto 0); @@ -55,25 +65,30 @@ begin Address_to_DMA <= (others => '0'); Size_to_DMA <= (others => '0'); Cmd_rs1_sig <= (others => '0'); - Cmd_rs1_sig <= (others => '0'); + Cmd_rs2_sig <= (others => '0'); Cmd_inst_funct_sig <= (others => '0'); elsif rising_edge(clk) then +--------------------Send to the DMA-------------------------------- + + if((cmd_valid_sig = '1') and (Cmd_rs2_sig(LENGTH downto 0) > Data_trans_from_DMA)) then + if Cmd_inst_funct = std_logic_vector(to_unsigned(30, 7)) then --#define DMA_WRITE_TO_RAM 30 /// 0X1E + Funct_to_DMA <= "0001111"; + elsif Cmd_inst_funct = std_logic_vector(to_unsigned(31, 7))then--"001111" then --#define DMA_READ_FROM_RAM 31 /// 0X1F + Funct_to_DMA <= "1111111"; + else + Funct_to_DMA <= (others => '0'); + end if; + Address_to_DMA <= Cmd_rs1_sig(INST_SIZE downto 0); + Size_to_DMA <= Cmd_rs2_sig(LENGTH downto 0); --------------------Reading from RoCC-------------------------------- - if (cmd_valid = '1') then + elsif (cmd_valid = '1') then Cmd_rs1_sig <= Cmd_rs1; Cmd_rs2_sig <= Cmd_rs2; --size 4 downto 0 [5bits] Cmd_inst_funct_sig <= Cmd_inst_funct; cmd_valid_sig <= '1'; - end if; ---------------------Send to the DMA-------------------------------- - - if(cmd_valid_sig = '1' and Cmd_rs2_sig(4 downto 0) > Data_trans_from_DMA) then - Funct_to_DMA <= Cmd_inst_funct_sig; - Address_to_DMA <= Cmd_rs1_sig(6 downto 0); - Size_to_DMA <= Cmd_rs2_sig(4 downto 0); else cmd_valid_sig <= '0'; Cmd_rs1_sig <= (others => '0'); diff --git a/SINGLE_PORT_RAM.vhd b/SINGLE_PORT_RAM.vhd index 5bb6b8c..04fa7f6 100644 --- a/SINGLE_PORT_RAM.vhd +++ b/SINGLE_PORT_RAM.vhd @@ -4,21 +4,28 @@ use ieee.numeric_std.all; ----------------------RAM Entity--------------------------- entity Single_Port_RAM is + generic ( + DATA_SIZE : integer := 7; -- Default source ID should be changed + ADDRESS_SIZE : integer := 6 -- Default destination ID should be changed + ); + --constant DATA_SIZE : integer := 7; -- Define constant for vector size for data of 8 bits + --constant ADDRESS_SIZE : integer := 6; -- Define constant for vector size for address 7 bits port( clk : in std_logic; rst : in std_logic; - Address_bus : in std_logic_vector(7 downto 0); --From DMA - Read_write_Enable : in std_logic_vector(1 downto 0); --From DMA - Data_bus_in : in std_logic_vector(7 downto 0); --From Noc - Data_bus_out : out std_logic_vector(7 downto 0) --From Noc - ); + Address_bus : in std_logic_vector(ADDRESS_SIZE downto 0); -- From DMA + Read_Enable : in std_logic; -- From DMA + Write_Enable : in std_logic; -- From DMA + Data_bus_in : in std_logic_vector(DATA_SIZE downto 0); -- From NoC + Data_bus_out : out std_logic_vector(DATA_SIZE downto 0) -- From NoC + ); end entity; ----------------------RAM Behaviour------------------------ architecture Single_Port_RAM_behav of Single_Port_RAM is ------- define the new type for the 128x8 RAM - type RAM_ARRAY is array (0 to 127 ) of std_logic_vector (7 downto 0); + type RAM_ARRAY is array (0 to 127 ) of std_logic_vector (DATA_SIZE downto 0); -------- initial values in the RAM to X00 signal RAM: RAM_ARRAY := (others=>x"00"); signal initialized : std_logic; -- Initialization flag @@ -26,22 +33,24 @@ architecture Single_Port_RAM_behav of Single_Port_RAM is begin process(clk, rst) begin - if rst = '0' then -- inverted reset + if rst = '0' then -- inverted reset Data_bus_out <= (others => '0'); initialized <= '1'; elsif rising_edge(clk) then - --Setting value to the RAM to coresponding index + --Setting value to the RAM to coresponding index_testing purpouse + -- synthesis translate_off if initialized = '1' then for i in 0 to 127 loop RAM(i) <= std_logic_vector(to_unsigned(i,8)); end loop; initialized <= '0'; end if; + -- synthesis translate_on --Read Write functionality of RAM - if (Read_write_Enable(0) = '0' and Read_write_Enable(1) = '1' )then --read enable; [MSB] READ Enable [LSB] WRITE Enable - Data_bus_out <= RAM(to_integer(unsigned(Address_bus(6 downto 0 )))); -- read data from RAM - elsif (Read_write_Enable(0) = '1' and Read_write_Enable(1) = '0') then --write enable; [MSB] READ Enable [LSB] WRITE Enable - RAM(to_integer(unsigned(Address_bus(6 downto 0)))) <= Data_bus_in(7 downto 0); -- Write data to RAM + if (Read_Enable = '1' and Write_Enable = '0' )then --read enable; [MSB] READ Enable [LSB] WRITE Enable + Data_bus_out <= RAM(to_integer(unsigned(Address_bus(ADDRESS_SIZE downto 0 )))); -- read data from RAM + elsif (Read_Enable = '0' and Write_Enable = '1') then --write enable; [MSB] READ Enable [LSB] WRITE Enable + RAM(to_integer(unsigned(Address_bus(ADDRESS_SIZE downto 0)))) <= Data_bus_in(DATA_SIZE downto 0); -- Write data to RAM Data_bus_out <= (others => '0'); else Data_bus_out <= (others => '0');