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updating dma TB

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root 2024-12-16 23:30:08 +01:00
parent db822d681c
commit eceea6c381
1 changed files with 3 additions and 49 deletions
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52
FULL_DMA_tb.vhd
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@ -15,12 +15,7 @@ architecture fulldmatb_arch of fulldmatb is
constant LENGTH : natural := 4; -- Define constant for vector size for size of Id's 5 bits
constant PACKET : natural := 31; -- Define constant for vector size for size of packet 32 bits
constant REG_SIZE : natural := 63; -- Define constant for vector size for size of Reg 64 bits
constant DMA_WRITE_TO_RAM : std_logic_vector(6 downto 0) := std_logic_vector(to_unsigned(15, 7)); --"0001111";
constant DMA_READ_TO_RAM : std_logic_vector(6 downto 0) := std_logic_vector(to_unsigned(127, 7)); --"1111111";
-- constant SOURCE_ID_int1 : integer := 1;
-- constant DEST_ID_int1 : integer := 0;
-- constant SOURCE_ID_int2 : integer := 0;
-- constant DEST_ID_int2 : integer := 1;
---- type flit_vector is array (natural range <>) of std_logic_vector(31 downto 0);
@ -178,9 +173,7 @@ begin
local_noc_tx => local_tx_sig2,
local_vc_write_tx_noc => local_vc_write_tx_sig2,
local_incr_tx_vec_noc => local_incr_tx_vec_sig2
-- local_incr_rx_vec_noc => local_incr_tx_vec_sig(1 sll (SOURCE_ID_inst2 + 1)),
-- local_noc_tx => local_tx_sig(SOURCE_ID_inst2),
-- local_vc_write_rx_noc => local_vc_write_tx_sig(1 sll (SOURCE_ID_inst2 + 1))
);
full_noc_inst1 : full_noc
@ -210,27 +203,22 @@ begin
--rx
local_rx_sig(1) <= local_tx_sig1;
local_vc_write_rx_sig(4) <= local_vc_write_tx_sig1;
--local_incr_rx_vec_sig(0) <= local_incr_tx_vec_sig1;
--tx
local_rx_sig1 <= local_tx_sig(1);
local_vc_write_rx_sig1 <= local_vc_write_tx_sig(4);
--local_incr_rx_vec_sig1 <= local_incr_tx_vec_sig(4);
--inst2 [rx_dma <= tx_noc] & [rx_noc <= tx_dma] source zero[0]
-- rx
local_rx_sig(0) <= local_tx_sig2;
local_vc_write_rx_sig(0) <= local_vc_write_tx_sig2;
--local_incr_rx_vec_sig(4) <= local_incr_tx_vec_sig2;
--tx destination one[1]
local_rx_sig2 <= local_tx_sig(0);
local_vc_write_rx_sig2 <= local_vc_write_tx_sig(0);
--local_incr_rx_vec_sig2 <= local_incr_tx_vec_sig(0);
-- Simulation process to assign values to CtrlCommand
simproc: process
begin
-- local_vc_write_tx_noc2 <= '0';
cmd_valid <= '0';
rst_tb <= '0';
wait for 10 ns;
@ -238,8 +226,7 @@ begin
wait for 40 ns;
-----------------------------------------------Test1---------------------------------------------------
-- cmd_inst_funct2 <= std_logic_vector(to_unsigned(15, 7)); -- --#define DMA_WRITE_TO_RAM 30 /// 0X1E
-- cmd_inst_funct1 <= std_logic_vector(to_unsigned(127, 7)); -- --#define DMA_READ_FROM_RAM 31 /// 0X1F
cmd_inst_funct2 <= "0011110"; --#define DMA_WRITE_TO_RAM 30 /// 0X1E
cmd_inst_funct1 <= "0011111"; --#define DMA_READ_FROM_RAM 31 /// 0X1F
@ -269,39 +256,6 @@ begin
end if;
end loop;
wait for 20 ns;
----------------------------------------------Test2------------------------------------------------------
-- cmd_inst_funct2 <= std_logic_vector(to_unsigned(15, 7)); -- --#define DMA_WRITE_TO_RAM 30 /// 0X1E
-- cmd_inst_funct1 <= std_logic_vector(to_unsigned(127, 7)); -- --#define DMA_READ_FROM_RAM 31 /// 0X1F
cmd_inst_funct1 <= "0011110"; --#define DMA_WRITE_TO_RAM 30 /// 0X1E
cmd_inst_funct2 <= "0011111"; --#define DMA_READ_FROM_RAM 31 /// 0X1F
cmd_rs1_2 <= std_logic_vector(to_unsigned(0, 57)) & "0000010"; --7 bit address & 57 bit zeros
cmd_rs1_1 <= std_logic_vector(to_unsigned(0, 57)) & "0001000"; --7 bit address & 57 bit zeros
cmd_rs2_2 <= std_logic_vector(to_unsigned(0, 59)) & "00100"; --5 bit size & 59 bit zeros
cmd_rs2_1 <= std_logic_vector(to_unsigned(0, 59)) & "00100"; --5 bit size & 59 bit zeros
wait for 20 ns;
cmd_valid <= '1';
wait for 40 ns;
cmd_valid <= '0';
-- local_vc_write_tx_noc2 <= '1';
wait for 180 ns;
-- local_vc_write_tx_noc2 <= '0';
for i in 0 to to_integer(unsigned(cmd_rs2_1)) loop
if(ram_sig1(to_integer(unsigned(cmd_rs1_1)) + i ) /= ram_sig2(to_integer(unsigned(cmd_rs1_2)) + i)) then
report "Test is failed: memory elements are not equal at location " &
"cmd_rs1_1 = " & integer'image(to_integer(unsigned(cmd_rs1_1)+i)) &
", cmd_rs1_2 = " & integer'image(to_integer(unsigned(cmd_rs1_2)+i))
severity note;
failed_status_test1 <= '1';
exit; -- Exit the loop
end if;
end loop;
wait for 20 ns;
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