library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; ----------------------Full DMA Entity--------------------------- entity Full_DMA is generic ( SOURCE_ID_NEW : std_logic_vector(5 downto 0) := "000000"; -- Default source ID should be changed DEST_ID_NEW : std_logic_vector(5 downto 0) := "000001" -- Default destination ID should be changed ); port( clk : in std_logic; rst : in std_logic; local_noc_rx : in std_logic_vector(31 downto 0);--- --From Noc local_vc_write_tx_noc : in std_logic; ---_vector(192-1 downto 0);--From NoC cmd_valid : in std_logic; --From Core Cmd_inst_funct : in std_logic_vector(6 downto 0); --From Core Cmd_inst_opcode : in std_logic_vector(6 downto 0); --From Core Cmd_inst_rd : in std_logic_vector(4 downto 0); --From Core Cmd_inst_rs1 : in std_logic_vector(4 downto 0); --From Core Cmd_inst_rs2 : in std_logic_vector(4 downto 0); --From Core Cmd_inst_xd : in std_logic; --From Core Cmd_inst_xs1 : in std_logic; --From Core Cmd_inst_xs2 : in std_logic; --From Core Cmd_rs1 : in std_logic_vector(63 downto 0); --From Core Cmd_rs2 : in std_logic_vector(63 downto 0); --From Core Cmd_busy : out std_logic; --To Core Cmd_ready : out std_logic; --To Core --always one local_noc_tx : out std_logic_vector(31 downto 0);--- --To NoC local_vc_write_rx_noc : out std_logic ---_vector(192-1 downto 0);--To NoC ); end entity; ----------------------Full DMA Behaviour------------------------ architecture Full_DMA_Arch of Full_DMA is component Single_Port_RAM is port( clk : in std_logic; rst : in std_logic; Address_bus : in std_logic_vector(7 downto 0); --From DMA Read_write_Enable : in std_logic_vector(1 downto 0); --From DMA Data_bus_in : in std_logic_vector(7 downto 0); --From Noc Data_bus_out : out std_logic_vector(7 downto 0) --From Noc ); end component; component Noc_Interface is generic ( SOURCE_ID : std_logic_vector(5 downto 0) := "000000"; -- Default source ID should be changed DEST_ID : std_logic_vector(5 downto 0) := "000001" -- Default destination ID should be changed ); port( clk : in std_logic; rst : in std_logic; Sent_valid_from_DMA : in std_logic; --From DMA Data_bus_noc_in : in std_logic_vector(7 downto 0); --From RAM tx_packet_length_noc : in std_logic_vector(4 downto 0); --From DMA local_noc_rx : in std_logic_vector(31 downto 0);--- --From Noc local_vc_write_tx_noc: in std_logic; ---_vector(192-1 downto 0);--From NoC rx_packet_length_noc : out std_logic_vector(4 downto 0); --To DMA local_noc_tx : out std_logic_vector(31 downto 0);--- --To NoC local_vc_write_rx_noc: out std_logic; ---_vector(192-1 downto 0);--To NoC Receive_valid_to_DMA : out std_logic; --To DMA Sent_Ack_to_DMA : out std_logic_vector(4 downto 0);-----------To DMA Data_bus_noc_out : out std_logic_vector(7 downto 0) --To RAM ); end component; component RoCC_Interface is port( clk : in std_logic; rst : in std_logic; cmd_valid : in std_logic; --From Core Cmd_inst_funct : in std_logic_vector(6 downto 0); --From Core Cmd_inst_opcode : in std_logic_vector(6 downto 0); --From Core Cmd_inst_rd : in std_logic_vector(4 downto 0); --From Core Cmd_inst_rs1 : in std_logic_vector(4 downto 0); --From Core Cmd_inst_rs2 : in std_logic_vector(4 downto 0); --From Core Cmd_inst_xd : in std_logic; --From Core Cmd_inst_xs1 : in std_logic; --From Core Cmd_inst_xs2 : in std_logic; --From Core Cmd_rs1 : in std_logic_vector(63 downto 0); --From Core Cmd_rs2 : in std_logic_vector(63 downto 0); --From Core Data_trans_from_DMA : in std_logic_vector(4 downto 0); --From DMA Cmd_busy : out std_logic; --To Core Cmd_ready : out std_logic; --To Core --always one Funct_to_DMA : out std_logic_vector(6 downto 0); --To DMA Address_to_DMA : out std_logic_vector(6 downto 0); --To DMA Size_to_DMA : out std_logic_vector(4 downto 0) --To DMA ); end component; component DMA_Controller is port( clk : in std_logic; rst : in std_logic; rx_packet_length_noc_to_DMA : in std_logic_vector(4 downto 0); --To DMA From Noc Receive_valid_to_DMA_from_Noc : in std_logic; --To DMA From Noc Sent_Ack_to_DMA_from_Noc : in std_logic_vector(4 downto 0);--------To DMA From Noc Funct_core_to_DMA : in std_logic_vector(6 downto 0); --To DMA From Core Address_core_to_DMA : in std_logic_vector(6 downto 0); --To DMA From Core Size_core_to_DMA : in std_logic_vector(4 downto 0); --To DMA From Core Address_bus_From_DMA : out std_logic_vector(7 downto 0); --From DMA To RAM Read_write_Enable_From_DMA : out std_logic_vector(1 downto 0); --From DMA To RAM Sent_valid_from_DMA_to_NoC : out std_logic; --From DMA To NoC tx_packet_length_noc_From_DMA : out std_logic_vector(4 downto 0); --From DMA To NoC Data_trans_from_DMA_to_core : out std_logic_vector(4 downto 0) --From DMA To Core ); end component; signal Address_bus_sig : std_logic_vector(7 downto 0); signal Read_write_Enable_sig : std_logic_vector(1 downto 0); signal Data_bus_in_sig : std_logic_vector(7 downto 0); signal Data_bus_out_sig : std_logic_vector(7 downto 0); signal Sent_valid_from_DMA_sig : std_logic; signal Data_bus_noc_in_sig : std_logic_vector(7 downto 0); signal tx_packet_length_noc_sig : std_logic_vector(4 downto 0); signal rx_packet_length_noc_sig : std_logic_vector(4 downto 0); signal local_noc_tx_sig : std_logic_vector(31 downto 0); signal local_vc_write_rx_noc_sig : std_logic; signal Receive_valid_to_DMA_sig : std_logic; signal Sent_Ack_to_DMA_sig : std_logic_vector(4 downto 0); signal Data_bus_noc_out_sig : std_logic_vector(7 downto 0); signal Data_trans_from_DMA_sig : std_logic_vector(4 downto 0); signal Funct_to_DMA_sig : std_logic_vector(6 downto 0); signal Address_to_DMA_sig : std_logic_vector(6 downto 0); signal Size_to_DMA_sig : std_logic_vector(4 downto 0); signal rx_packet_length_noc_to_DMA_sig : std_logic_vector(4 downto 0); signal Receive_valid_to_DMA_from_Noc_sig : std_logic; signal Sent_Ack_to_DMA_from_Noc_sig : std_logic_vector(4 downto 0); signal Funct_core_to_DMA_sig : std_logic_vector(6 downto 0); signal Address_core_to_DMA_sig : std_logic_vector(6 downto 0); Signal Size_core_to_DMA_sig : std_logic_vector(4 downto 0); signal Address_bus_From_DMA_sig : std_logic_vector(7 downto 0); signal Read_write_Enable_From_DMA_sig : std_logic_vector(1 downto 0); signal Sent_valid_from_DMA_to_NoC_sig : std_logic; signal tx_packet_length_noc_From_DMA_sig : std_logic_vector(4 downto 0); signal Data_trans_from_DMA_to_core_sig : std_logic_vector(4 downto 0); begin -- Single_Port_RAM mapping Single_Port_RAM_inst : Single_Port_RAM port map( clk => clk, rst => rst, Address_bus => Address_bus_sig, Read_write_Enable => Read_write_Enable_sig, Data_bus_in => Data_bus_in_sig, -- Assuming data input comes from NoC Data_bus_out => Data_bus_out_sig ); -- Noc_Interface mapping Noc_Interface_inst : Noc_Interface generic map ( SOURCE_ID => SOURCE_ID_NEW, DEST_ID => DEST_ID_NEW ) port map( clk => clk, rst => rst, Sent_valid_from_DMA => Sent_valid_from_DMA_sig, Data_bus_noc_in => Data_bus_in_sig, tx_packet_length_noc => tx_packet_length_noc_sig, local_noc_rx => local_noc_rx, --- local_vc_write_tx_noc=> local_vc_write_tx_noc, --- rx_packet_length_noc => rx_packet_length_noc_sig, local_noc_tx => local_noc_tx, --- local_vc_write_rx_noc=> local_vc_write_rx_noc, --- Receive_valid_to_DMA => Receive_valid_to_DMA_sig, Sent_Ack_to_DMA => Sent_Ack_to_DMA_sig, Data_bus_noc_out => Data_bus_out_sig ); -- RoCC_Interface mapping RoCC_Interface_inst : RoCC_Interface port map( clk => clk, rst => rst, cmd_valid => cmd_valid, --- Cmd_inst_funct => Cmd_inst_funct, --- Cmd_inst_opcode => Cmd_inst_opcode, --- Cmd_inst_rd => Cmd_inst_rd, --- Cmd_inst_rs1 => Cmd_inst_rs1, --- Cmd_inst_rs2 => Cmd_inst_rs2, --- Cmd_inst_xd => Cmd_inst_xd, --- Cmd_inst_xs1 => Cmd_inst_xs1, --- Cmd_inst_xs2 => Cmd_inst_xs2, --- Cmd_rs1 => Cmd_rs1, --- Cmd_rs2 => Cmd_rs2, --- Data_trans_from_DMA => Data_trans_from_DMA_sig, Cmd_busy => Cmd_busy, --- Cmd_ready => Cmd_ready, --- Funct_to_DMA => Funct_to_DMA_sig, Address_to_DMA => Address_to_DMA_sig, Size_to_DMA => Size_to_DMA_sig ); -- DMA_Controller mapping DMA_Controller_inst : DMA_Controller port map( clk => clk, rst => rst, rx_packet_length_noc_to_DMA => rx_packet_length_noc_to_DMA_sig, Receive_valid_to_DMA_from_Noc => Receive_valid_to_DMA_from_Noc_sig, Sent_Ack_to_DMA_from_Noc => Sent_Ack_to_DMA_from_Noc_sig, Funct_core_to_DMA => Funct_core_to_DMA_sig, Address_core_to_DMA => Address_core_to_DMA_sig, Size_core_to_DMA => Size_core_to_DMA_sig, Address_bus_From_DMA => Address_bus_From_DMA_sig, Read_write_Enable_From_DMA => Read_write_Enable_From_DMA_sig, Sent_valid_from_DMA_to_NoC => Sent_valid_from_DMA_to_NoC_sig, tx_packet_length_noc_From_DMA => tx_packet_length_noc_From_DMA_sig, Data_trans_from_DMA_to_core => Data_trans_from_DMA_to_core_sig ); ----mapping need to be done yet-------------