library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; ---vsim -gui work.fulldmatb entity fulldmaTB is end entity; architecture fulldmaTB_arch of fulldmaTB is constant DATA_SIZE : integer := 7; -- Define constant for vector size for data of 8 bits constant INST_SIZE : integer := 6; -- Define constant for vector size for inst of 6 bits constant LENGTH : integer := 4; -- Define constant for vector size for size of Id's 5 bits constant PACKET : integer := 31; -- Define constant for vector size for size of packet 32 bits constant REG_SIZE : integer := 63; -- Define constant for vector size for size of Reg 64 bits component Full_DMA is generic ( DATA_SIZE : integer := 7; -- Define constant for vector size for data of 8 bits INST_SIZE : integer := 6; -- Define constant for vector size for inst of 6 bits LENGTH : integer := 4; -- Define constant for vector size for size of Id's 5 bits PACKET : integer := 31; -- Define constant for vector size for size of packet 32 bits REG_SIZE : integer := 63; -- Define constant for vector size for size of Reg 64 bits SOURCE_ID_NEW : std_logic_vector(5 downto 0) := "000000"; -- Default source ID should be changed DEST_ID_NEW : std_logic_vector(5 downto 0) := "000001" -- Default destination ID should be changed ); port( clk : in std_logic; rst : in std_logic; local_noc_rx : in std_logic_vector(PACKET downto 0);--- --From Noc local_vc_write_tx_noc : in std_logic; ---_vector(192-1 downto 0);--From NoC cmd_valid : in std_logic; --From Core Cmd_inst_funct : in std_logic_vector(INST_SIZE downto 0); --From Core Cmd_inst_opcode : in std_logic_vector(INST_SIZE downto 0); --From Core Cmd_inst_rd : in std_logic_vector(LENGTH downto 0); --From Core Cmd_inst_rs1 : in std_logic_vector(LENGTH downto 0); --From Core Cmd_inst_rs2 : in std_logic_vector(LENGTH downto 0); --From Core Cmd_inst_xd : in std_logic; --From Core Cmd_inst_xs1 : in std_logic; --From Core Cmd_inst_xs2 : in std_logic; --From Core Cmd_rs1 : in std_logic_vector(REG_SIZE downto 0); --From Core Cmd_rs2 : in std_logic_vector(REG_SIZE downto 0); --From Core Cmd_busy : out std_logic; --To Core Cmd_ready : out std_logic; --To Core --always one local_noc_tx : out std_logic_vector(PACKET downto 0);--- --To NoC local_vc_write_rx_noc : out std_logic ---_vector(192-1 downto 0); --To NoC ); end component; signal clk_tb : std_logic; signal rst_tb : std_logic; signal local_noc_rx1, local_noc_rx2 : std_logic_vector(PACKET downto 0); signal local_vc_write_tx_noc1 : std_logic; signal cmd_valid,local_vc_write_tx_noc2 : std_logic; signal Cmd_inst_funct1,Cmd_inst_funct2 : std_logic_vector(INST_SIZE downto 0); signal Cmd_inst_opcode : std_logic_vector(INST_SIZE downto 0); signal Cmd_inst_rd : std_logic_vector(LENGTH downto 0); signal Cmd_inst_rs1 : std_logic_vector(LENGTH downto 0); signal Cmd_inst_rs2 : std_logic_vector(LENGTH downto 0); signal Cmd_inst_xd : std_logic; signal Cmd_inst_xs1 : std_logic; signal Cmd_inst_xs2 : std_logic; signal Cmd_rs1_1, Cmd_rs1_2 : std_logic_vector(REG_SIZE downto 0); signal Cmd_rs2_1, Cmd_rs2_2 : std_logic_vector(REG_SIZE downto 0); signal Cmd_busy : std_logic; signal Cmd_ready : std_logic; signal local_noc_tx1, local_noc_tx2 : std_logic_vector(PACKET downto 0); signal local_vc_write_rx_noc : std_logic; begin -- Component instantiation with a label fulldma_inst1 : Full_DMA generic map ( SOURCE_ID_NEW => "000001", -- Set source ID DEST_ID_NEW => "000000" -- Set destination ID ) port map ( clk => clk_tb, rst => rst_tb, local_noc_rx => local_noc_rx1, local_vc_write_tx_noc => local_vc_write_tx_noc1, cmd_valid => cmd_valid, Cmd_inst_funct => Cmd_inst_funct1, Cmd_inst_opcode => Cmd_inst_opcode, Cmd_inst_rd => Cmd_inst_rd, Cmd_inst_rs1 => Cmd_inst_rs1, Cmd_inst_rs2 => Cmd_inst_rs2, Cmd_inst_xd => Cmd_inst_xd, Cmd_inst_xs1 => Cmd_inst_xs1, Cmd_inst_xs2 => Cmd_inst_xs2, Cmd_rs1 => Cmd_rs1_1, Cmd_rs2 => Cmd_rs2_1, Cmd_busy => Cmd_busy, Cmd_ready => Cmd_ready, local_noc_tx => local_noc_tx1, local_vc_write_rx_noc => local_vc_write_rx_noc ); -- Component instantiation with a label fulldma_inst2 : Full_DMA generic map ( SOURCE_ID_NEW => "000000", -- Set source ID DEST_ID_NEW => "000001" -- Set destination ID ) port map ( clk => clk_tb, rst => rst_tb, local_noc_rx => local_noc_rx2, local_vc_write_tx_noc => local_vc_write_tx_noc2, cmd_valid => cmd_valid, Cmd_inst_funct => Cmd_inst_funct2, Cmd_inst_opcode => Cmd_inst_opcode, Cmd_inst_rd => Cmd_inst_rd, Cmd_inst_rs1 => Cmd_inst_rs1, Cmd_inst_rs2 => Cmd_inst_rs2, Cmd_inst_xd => Cmd_inst_xd, Cmd_inst_xs1 => Cmd_inst_xs1, Cmd_inst_xs2 => Cmd_inst_xs2, Cmd_rs1 => Cmd_rs1_2, Cmd_rs2 => Cmd_rs2_2, Cmd_busy => Cmd_busy, Cmd_ready => Cmd_ready, local_noc_tx => local_noc_tx2, local_vc_write_rx_noc => local_vc_write_rx_noc ); -- Clock generation process clk_process: process begin clk_tb <= '0'; wait for 5 ns; clk_tb <= '1'; wait for 5 ns; end process; -----------------------NoC connection has to be changed-------------------- local_noc_rx1 <= local_noc_tx2; local_noc_rx2 <= local_noc_tx1; -- Simulation process to assign values to CtrlCommand simproc: process begin local_vc_write_tx_noc2 <= '0'; cmd_valid <= '0'; rst_tb <= '0'; wait for 10 ns; rst_tb <= '1'; wait for 40 ns; Cmd_inst_funct2 <= "0011110"; --#define DMA_WRITE_TO_RAM 30 /// 0X1E Cmd_inst_funct1 <= "0011111"; --#define DMA_READ_FROM_RAM 31 /// 0X1F Cmd_rs1_1 <= std_logic_vector(to_unsigned(0, 57)) & "0000010"; --7 bit address & 57 bit zeros Cmd_rs1_2 <= std_logic_vector(to_unsigned(0, 57)) & "0001000"; --7 bit address & 57 bit zeros Cmd_rs2_1 <= std_logic_vector(to_unsigned(0, 59)) & "00100"; --5 bit size & 59 bit zeros Cmd_rs2_2 <= std_logic_vector(to_unsigned(0, 59)) & "00100"; --5 bit size & 59 bit zeros wait for 20 ns; cmd_valid <= '1'; wait for 40 ns; cmd_valid <= '0'; local_vc_write_tx_noc2 <= '1'; wait for 80 ns; local_vc_write_tx_noc2 <= '0'; wait for 1000 ns; -- wait for 1000 ns ; end process; end architecture;