-- Header structure: ----------------------------------------------------------------------------------------------------- --| | | 2bit | 2bit | 2bit | 2bit | 2bit | 2bit | | --| Flit_padding | Packet_id | Z_src | Y_src | X_src | Z_dest | Y_dest | X_dest | Packet_length | --|31 3bits 29|28 12 bits 17|16 6bits 11|10 6bits 5|4 5bits 0| ----------------------------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; ----------------------NoC Interface Entity--------------------------- entity Noc_Interface is -- constant DATA_SIZE : integer := 7; -- Define constant for vector size for data of 8 bits -- constant LENGTH : integer := 4; -- Define constant for vector size for size of Id's 5 bits -- constant PACKET : integer := 11; -- Define constant for vector size for size of Id's 12 bits -- constant REG_SIZE : integer := 31; -- Define constant for vector size for size of Reg 31 bits generic ( DATA_SIZE : integer := 7; -- Define constant for vector size for data of 8 bits LENGTH : integer := 4; -- Define constant for vector size for size of Id's 5 bits PACKET : integer := 11; -- Define constant for vector size for size of Id's 12 bits REG_SIZE : integer := 31; -- Define constant for vector size for size of Reg 31 bits SOURCE_ID : std_logic_vector(5 downto 0) := "000000"; -- Default source ID should be changed DEST_ID : std_logic_vector(5 downto 0) := "000001" -- Default destination ID should be changed ); port( clk : in std_logic; rst : in std_logic; Sent_valid_from_DMA : in std_logic; --From DMA Data_bus_noc_in : in std_logic_vector(DATA_SIZE downto 0); --From RAM tx_packet_length_noc : in std_logic_vector(LENGTH downto 0); --From DMA local_noc_rx : in std_logic_vector(REG_SIZE downto 0);--- --From Noc local_vc_write_tx_noc: in std_logic; ---_vector(192-1 downto 0);--From NoC rx_packet_length_noc : out std_logic_vector(LENGTH downto 0); --To DMA local_noc_tx : out std_logic_vector(REG_SIZE downto 0);--- --To NoC local_vc_write_rx_noc: out std_logic; ---_vector(192-1 downto 0);--To NoC Receive_valid_to_DMA : out std_logic; --To DMA Sent_Ack_to_DMA : out std_logic_vector(LENGTH downto 0);-----------To DMA Data_bus_noc_out : out std_logic_vector(DATA_SIZE downto 0) --To RAM ); end entity; ----------------------NoC Interface Behaviour------------------------ architecture Noc_Interface_Arch of Noc_Interface is Signal packet_id : std_logic_vector(PACKET downto 0); signal count : std_logic_vector(LENGTH downto 0); signal Sent_packet : std_logic_vector(LENGTH downto 0); signal packet_len : std_logic_vector(LENGTH downto 0); --signal packet_length : std_logic_vector(4 downto 0); begin rxprocess : process(clk, rst) begin if rst = '0' then rx_packet_length_noc <= (others => '0'); local_noc_tx <= (others => '0'); local_vc_write_rx_noc <= '0'; Receive_valid_to_DMA <= '0'; Sent_Ack_to_DMA <= (others => '0'); Data_bus_noc_out <= (others => '0'); count <= (others => '0'); Sent_packet <= (others => '0'); packet_id <= (others => '0'); packet_len <= (others => '0'); elsif rising_edge(clk) then --------------------Reading from NoC-------------------------------- if (local_vc_write_tx_noc = '1') then if (local_noc_rx(31 downto 29) = "100") then rx_packet_length_noc <= local_noc_rx(LENGTH downto 0 ); --packet length packet_len <= local_noc_rx(LENGTH downto 0 ); --packet length count <= (others => '0'); --counter reset packet_id <= local_noc_rx(28 downto 17); --current packetid Receive_valid_to_DMA <= '1'; elsif(unsigned(count) <= unsigned(packet_len) and unsigned(packet_len) > 0) then report "Receive_valid_to_DMA is 1 from Line 80"; Receive_valid_to_DMA <= '1'; --valid to DMA count <= std_logic_vector(unsigned(count) + 1); --counter update Data_bus_noc_out <= local_noc_rx(DATA_SIZE downto 0 ); --NoC is given to RAM else report "Receive_valid_to_DMA is 0 from Line 86"; packet_len <= (others=>'0'); Receive_valid_to_DMA <= '0'; Data_bus_noc_out <= (others=>'0'); count <= (others=>'0'); end if; --------------------Writing to NoC---------------------------------- elsif ((Sent_valid_from_DMA = '1') and (to_integer(unsigned(tx_packet_length_noc)) >= 0)) then -- the valid from dma is one cycle behind if(Sent_packet = "00000") then --Sent_Ack_to_DMA <= std_logic_vector(unsigned(Sent_packet) + 1); --to DMA updated value Sent_packet <= std_logic_vector(unsigned(Sent_packet) + 1); --updating packet id local_noc_tx <= "100" & packet_id & SOURCE_ID & DEST_ID & tx_packet_length_noc; local_vc_write_rx_noc <= '1'; else Sent_Ack_to_DMA <= Sent_packet;--std_logic_vector(unsigned(Sent_packet) + 1); --to DMA updated value Sent_packet <= std_logic_vector(unsigned(Sent_packet) + 1); local_noc_tx <= std_logic_vector(to_unsigned(0, 24)) & Data_bus_noc_in; --24bit zeros in msb and 8 bit data local_vc_write_rx_noc <= '1'; end if; else rx_packet_length_noc <= (others => '0'); local_noc_tx <= (others => '0'); local_vc_write_rx_noc <= '0'; Receive_valid_to_DMA <= '0'; Sent_Ack_to_DMA <= (others => '0'); Data_bus_noc_out <= (others => '0'); count <= (others => '0'); Sent_packet <= (others => '0'); end if; end if; end process; end architecture;