-- Execute custom RISC-V instructions structure:
----------------------------------------------------------------------------------------
--|    7bits     |     5bits   |   6bits    |  1bit |  1bit  |  1bit |   5bit |   7bit |
--|    Funct     |     rs2     |    rs1     |   xd  |  xs1   |  xs2  |   rd   | opcode | 
--|31          25|24         20|19        15|   14  |  13    |  12   |11     7|6      0|
----------------------------------------------------------------------------------------
--ROCC_INSTRUCTION_RS1_RS2(x, rs1, rs2, funct) variables avaliable for baremetalC is rs1,rs2-register address and funct-function
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

----------------------RoCC Interface Entity---------------------------
entity RoCC_Interface is
    -- constant INST_SIZE    : integer := 6;  -- Define constant for vector size for inst of 6 bits
    -- constant LENGTH       : integer := 4;  -- Define constant for vector size for size of Id's 5 bits
    -- constant PACKET       : integer := 11; -- Define constant for vector size for size of Id's 12 bits
    -- constant REG_SIZE     : integer := 63; -- Define constant for vector size for size of Reg 63 bits
    generic (
        INST_SIZE    : integer := 6;  -- Define constant for vector size for inst of 6 bits
        LENGTH       : integer := 4;  -- Define constant for vector size for size of Id's 5 bits
        PACKET       : integer := 11; -- Define constant for vector size for size of Id's 12 bits
        REG_SIZE     : integer := 63 -- Define constant for vector size for size of Reg 63 bits
    );
    port(
        clk                  : in  std_logic; 
        rst                  : in  std_logic;       
        cmd_valid            : in  std_logic;                                    --From Core
        Cmd_inst_funct       : in  std_logic_vector(INST_SIZE downto 0);         --From Core
        Cmd_inst_opcode      : in  std_logic_vector(INST_SIZE downto 0);         --From Core
        Cmd_inst_rd          : in  std_logic_vector(LENGTH    downto 0);         --From Core
        Cmd_inst_rs1         : in  std_logic_vector(LENGTH    downto 0);         --From Core
        Cmd_inst_rs2         : in  std_logic_vector(LENGTH    downto 0);         --From Core
        Cmd_inst_xd          : in  std_logic;                                    --From Core
        Cmd_inst_xs1         : in  std_logic;                                    --From Core
        Cmd_inst_xs2         : in  std_logic;                                    --From Core
        Cmd_rs1              : in  std_logic_vector(REG_SIZE downto 0);          --From Core
        Cmd_rs2              : in  std_logic_vector(REG_SIZE downto 0);          --From Core
        Data_trans_from_DMA  : in  std_logic_vector(LENGTH   downto 0);          --From DMA
        Cmd_busy             : out std_logic;                                    --To Core 
        Cmd_ready            : out std_logic;                                    --To Core --always one
        Funct_to_DMA         : out std_logic_vector(INST_SIZE downto 0);         --To DMA  
        Address_to_DMA       : out std_logic_vector(INST_SIZE downto 0);         --To DMA  
        Size_to_DMA          : out std_logic_vector(LENGTH    downto 0)          --To DMA  
        );
end entity;

----------------------Rocc Interface Behaviour------------------------

architecture RoCC_Interface_Arch of RoCC_Interface is
    Signal Cmd_rs1_sig         : std_logic_vector(REG_SIZE downto 0);
    signal Cmd_rs2_sig         : std_logic_vector(REG_SIZE downto 0);
    Signal Cmd_inst_funct_sig  : std_logic_vector(INST_SIZE downto 0);
    Signal cmd_valid_sig       : std_logic;
    --signal Sent_packet   : std_logic_vector(4 downto 0);
    --signal packet_length : std_logic_vector(4 downto 0);

begin
    process(clk, rst)
    begin
        if rst = '0' then
            Cmd_busy                 <= '0';                  
            Cmd_ready                <= '1';                --To Core --always one
            cmd_valid_sig            <= '0';
            Funct_to_DMA             <= (others => '0');        
            Address_to_DMA           <= (others => '0');       
            Size_to_DMA              <= (others => '0');
            Cmd_rs1_sig              <= (others => '0');
            Cmd_rs2_sig              <= (others => '0');
            Cmd_inst_funct_sig       <= (others => '0');

        elsif rising_edge(clk) then

--------------------Send to the DMA--------------------------------

            if((cmd_valid_sig = '1') and  (Cmd_rs2_sig(LENGTH downto 0) > Data_trans_from_DMA)) then
                if Cmd_inst_funct = std_logic_vector(to_unsigned(30, 7)) then    --#define DMA_WRITE_TO_RAM  30 /// 0X1E
                    Funct_to_DMA     <= "0001111";
                elsif Cmd_inst_funct = std_logic_vector(to_unsigned(31, 7))then--"001111" then --#define DMA_READ_FROM_RAM 31  /// 0X1F
                    Funct_to_DMA     <= "1111111";
                else 
                    Funct_to_DMA     <= (others => '0');
                end if;                
                Address_to_DMA       <= Cmd_rs1_sig(INST_SIZE downto 0);
                Size_to_DMA          <= Cmd_rs2_sig(LENGTH downto 0);
--------------------Reading from RoCC--------------------------------

            elsif (cmd_valid = '1') then
                Cmd_rs1_sig          <= Cmd_rs1; 
                Cmd_rs2_sig          <= Cmd_rs2; --size 4 downto 0 [5bits]
                Cmd_inst_funct_sig   <= Cmd_inst_funct;
                cmd_valid_sig        <= '1';
            else
                cmd_valid_sig        <= '0';
                Cmd_rs1_sig          <= (others => '0');
                Cmd_rs1_sig          <= (others => '0');
                Cmd_inst_funct_sig   <= (others => '0');

            end if;
        end if;
    end process;
end architecture;