library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

----------------------ram Entity---------------------------
entity single_port_ram is
    generic (
        DATA_SIZE      : natural := 7; -- Default source ID should be changed
        ADDRESS_SIZE   : natural := 6  -- Default destination ID should be changed
    );
    --constant DATA_SIZE    : integer := 7; -- Define constant for vector size for data of 8 bits
    --constant ADDRESS_SIZE : integer := 6; -- Define constant for vector size for address 7 bits   
    port(
        clk               : in  std_logic; 
        rst               : in  std_logic;
        address_bus       : in  std_logic_vector(ADDRESS_SIZE downto 0); -- From DMA
        read_enable       : in  std_logic;                               -- From DMA
        write_enable      : in  std_logic;                               -- From DMA
        data_bus_in       : in  std_logic_vector(DATA_SIZE downto 0); -- From NoC
        data_bus_out      : out std_logic_vector(DATA_SIZE downto 0)   -- From NoC
    );
end entity;

----------------------ram Behaviour------------------------
architecture single_port_ram_behav of single_port_ram is

   ------- define the new type for the 128x8 ram 
   type ram_array is array (0 to 127 ) of std_logic_vector (DATA_SIZE downto 0);
   -------- initial values in the ram to X00
   signal ram: ram_array := (others=>x"00"); 
   signal initialized : std_logic; -- Initialization flag

begin
    process(clk, rst)
    begin
        if rst = '0' then -- inverted reset 
            data_bus_out <= (others => '0');
            initialized <= '1';
        elsif rising_edge(clk) then
    --Setting value to the ram to coresponding index_testing purpouse  
    -- synthesis translate_off
            if initialized = '1' then
                for i in 0 to 127 loop
                    ram(i) <= std_logic_vector(to_unsigned(i,8));
                end loop;
                initialized <= '0';
            end if;
    -- synthesis translate_on
    --Read Write functionality of ram
            if (read_enable = '1' and write_enable = '0' )then               --read enable; [MSB] READ Enable [LSB] WRITE Enable  
                data_bus_out <=  ram(to_integer(unsigned(address_bus(ADDRESS_SIZE downto 0 ))));         -- read data from ram 
            elsif (read_enable = '0' and write_enable = '1') then             --write enable; [MSB] READ Enable [LSB] WRITE Enable 
                ram(to_integer(unsigned(address_bus(ADDRESS_SIZE downto 0)))) <= data_bus_in(DATA_SIZE downto 0); -- Write data to ram
                data_bus_out <= (others => '0');
            else
                data_bus_out <= (others => '0');
            end if;
        end if;
    end process;
end architecture;