library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.NOC_3D_PACKAGE.all; -- vcom -work work -2008 -explicit -stats=none D:/project_item_ids/DMA_VHDL/DMA_ARCH_MODULAR_DESGIN/FULL_DMA_tb.vhd ---vsim -gui work.fulldmatb entity fulldmatb is end entity; architecture fulldmatb_arch of fulldmatb is constant DATA_SIZE : natural := 7; -- Define constant for vector size for data of 8 bits constant INST_SIZE : natural := 6; -- Define constant for vector size for inst of 6 bits constant LENGTH : natural := 4; -- Define constant for vector size for size of Id's 5 bits constant PACKET : natural := 31; -- Define constant for vector size for size of packet 32 bits constant REG_SIZE : natural := 63; -- Define constant for vector size for size of Reg 64 bits ---- type flit_vector is array (natural range <>) of std_logic_vector(31 downto 0); component full_dma is generic ( DATA_SIZE : natural := 7; -- Define constant for vector size for data of 8 bits INST_SIZE : natural := 6; -- Define constant for vector size for inst of 6 bits LENGTH : natural := 4; -- Define constant for vector size for size of Id's 5 bits PACKET : natural := 31; -- Define constant for vector size for size of packet 32 bits REG_SIZE : natural := 63; -- Define constant for vector size for size of Reg 64 bits SOURCE_ID_NEW : std_logic_vector(5 downto 0) := "000000"; -- Default source ID should be changed DEST_ID_NEW : std_logic_vector(5 downto 0) := "000001" -- Default destination ID should be changed ); port( clk : in std_logic; rst : in std_logic; local_noc_rx : in std_logic_vector(PACKET downto 0);--- --From Noc local_vc_write_rx_noc : in std_logic; ---_vector(192-1 downto 0);--From NoC local_incr_rx_vec_noc : in std_logic; cmd_valid : in std_logic; --From Core cmd_inst_funct : in std_logic_vector(INST_SIZE downto 0); --From Core cmd_inst_opcode : in std_logic_vector(INST_SIZE downto 0); --From Core cmd_inst_rd : in std_logic_vector(LENGTH downto 0); --From Core cmd_inst_rs1 : in std_logic_vector(LENGTH downto 0); --From Core cmd_inst_rs2 : in std_logic_vector(LENGTH downto 0); --From Core cmd_inst_xd : in std_logic; --From Core cmd_inst_xs1 : in std_logic; --From Core cmd_inst_xs2 : in std_logic; --From Core cmd_rs1 : in std_logic_vector(REG_SIZE downto 0); --From Core cmd_rs2 : in std_logic_vector(REG_SIZE downto 0); --From Core cmd_busy : out std_logic; --To Core cmd_ready : out std_logic; --To Core --always one local_noc_tx : out std_logic_vector(PACKET downto 0);--- --To NoC local_vc_write_tx_noc : out std_logic; ---_vector(192-1 downto 0);--To NoC local_incr_tx_vec_noc : out std_logic --To NoC ); end component; component full_noc is port( clk, rst : in std_logic; local_rx : in flit_vector(48-1 downto 0); local_vc_write_rx : in std_logic_vector(192-1 downto 0); local_incr_rx_vec : in std_logic_vector(192-1 downto 0); local_tx : out flit_vector(48-1 downto 0); local_vc_write_tx : out std_logic_vector(192-1 downto 0); local_incr_tx_vec : out std_logic_vector(192-1 downto 0) ); end component; signal clk_tb : std_logic; signal rst_tb : std_logic; signal local_rx_sig : flit_vector(48-1 downto 0) := (others => (others => '0')); --map coressponding flit to port signal local_tx_sig : flit_vector(48-1 downto 0) := (others => (others => '0')); signal local_vc_write_rx_sig : std_logic_vector(192-1 downto 0) := (others => '0'); signal local_incr_rx_vec_sig : std_logic_vector(192-1 downto 0) := (others => '0'); signal local_vc_write_tx_sig : std_logic_vector(192-1 downto 0) := (others => '0'); signal local_incr_tx_vec_sig : std_logic_vector(192-1 downto 0) := (others => '0'); signal local_vc_write_tx_noc1 : std_logic; signal cmd_valid,local_vc_write_tx_noc2 : std_logic; signal cmd_inst_funct1,cmd_inst_funct2 : std_logic_vector(INST_SIZE downto 0); signal cmd_inst_opcode : std_logic_vector(INST_SIZE downto 0); signal cmd_inst_rd : std_logic_vector(LENGTH downto 0); signal cmd_inst_rs1 : std_logic_vector(LENGTH downto 0); signal cmd_inst_rs2 : std_logic_vector(LENGTH downto 0); signal cmd_inst_xd : std_logic; signal cmd_inst_xs1 : std_logic; signal cmd_inst_xs2 : std_logic; signal cmd_rs1_1, cmd_rs1_2 : std_logic_vector(REG_SIZE downto 0); signal cmd_rs2_1, cmd_rs2_2 : std_logic_vector(REG_SIZE downto 0); signal cmd_busy : std_logic; signal cmd_ready : std_logic; signal local_tx_sig1, local_tx_sig2 : std_logic_vector(PACKET downto 0);--- --To NoC signal local_rx_sig1, local_rx_sig2 : std_logic_vector(PACKET downto 0);--- --To NoC signal local_vc_write_rx_sig1, local_vc_write_rx_sig2 : std_logic; signal local_vc_write_tx_sig1, local_vc_write_tx_sig2 : std_logic; signal local_incr_tx_vec_sig1, local_incr_tx_vec_sig2 : std_logic; signal local_incr_rx_vec_sig1, local_incr_rx_vec_sig2 : std_logic; signal failed_status_test1 : std_logic := '0'; type ram_array is array (0 to 127 ) of std_logic_vector (DATA_SIZE downto 0); alias ram_sig1 is <>; alias ram_sig2 is <>; -- alias ram_sig1 is fulldma_inst1.single_port_ram_inst.ram : ram_array; begin -- Component instantiation with a label fulldma_inst1 : full_dma generic map ( SOURCE_ID_NEW => "000001", -- Set source ID DEST_ID_NEW => "000000" -- Set destination ID ) port map ( clk => clk_tb, rst => rst_tb, -- local_incr_tx_vec_noc => local_incr_tx_vec_sig(1 sll (DEST_ID_inst1 + 1)), -- local_noc_rx => local_rx_sig(DEST_ID_inst1), -- local_vc_write_tx_noc => local_vc_write_tx_sig(1 sll (DEST_ID_inst1 + 1)), local_noc_rx => local_rx_sig1, local_vc_write_rx_noc => local_vc_write_rx_sig1, local_incr_rx_vec_noc => local_incr_rx_vec_sig1, cmd_valid => cmd_valid, cmd_inst_funct => cmd_inst_funct1, cmd_inst_opcode => cmd_inst_opcode, cmd_inst_rd => cmd_inst_rd, cmd_inst_rs1 => cmd_inst_rs1, cmd_inst_rs2 => cmd_inst_rs2, cmd_inst_xd => cmd_inst_xd, cmd_inst_xs1 => cmd_inst_xs1, cmd_inst_xs2 => cmd_inst_xs2, cmd_rs1 => cmd_rs1_1, cmd_rs2 => cmd_rs2_1, cmd_busy => cmd_busy, cmd_ready => cmd_ready, local_noc_tx => local_tx_sig1, local_vc_write_tx_noc => local_vc_write_tx_sig1, local_incr_tx_vec_noc => local_incr_tx_vec_sig1 -- local_incr_rx_vec_noc => local_incr_tx_vec_sig(1 sll (SOURCE_ID_inst1 + 1)), -- local_noc_tx => local_tx_sig(SOURCE_ID_inst1), -- local_vc_write_rx_noc => local_vc_write_tx_sig(1 sll (SOURCE_ID_inst1 + 1)) ); -- Component instantiation with a label fulldma_inst2 : full_dma generic map ( SOURCE_ID_NEW => "000000", -- Set source ID DEST_ID_NEW => "000001" -- Set destination ID ) port map ( clk => clk_tb, rst => rst_tb, -- local_incr_tx_vec_noc => local_incr_tx_vec_sig(1 sll (DEST_ID_inst2 + 1)), -- local_noc_rx => local_rx_sig(DEST_ID_inst2), -- local_vc_write_tx_noc => local_vc_write_tx_sig(1 sll (DEST_ID_inst2 + 1)), local_noc_rx => local_rx_sig2, local_vc_write_rx_noc => local_vc_write_rx_sig2, local_incr_rx_vec_noc => local_incr_rx_vec_sig2, cmd_valid => cmd_valid, cmd_inst_funct => cmd_inst_funct2, cmd_inst_opcode => cmd_inst_opcode, cmd_inst_rd => cmd_inst_rd, cmd_inst_rs1 => cmd_inst_rs1, cmd_inst_rs2 => cmd_inst_rs2, cmd_inst_xd => cmd_inst_xd, cmd_inst_xs1 => cmd_inst_xs1, cmd_inst_xs2 => cmd_inst_xs2, cmd_rs1 => cmd_rs1_2, cmd_rs2 => cmd_rs2_2, cmd_busy => cmd_busy, cmd_ready => cmd_ready, local_noc_tx => local_tx_sig2, local_vc_write_tx_noc => local_vc_write_tx_sig2, local_incr_tx_vec_noc => local_incr_tx_vec_sig2 ); full_noc_inst1 : full_noc port map( clk => clk_tb, rst => rst_tb, local_rx => local_rx_sig, local_vc_write_rx => local_vc_write_rx_sig, local_incr_rx_vec => local_incr_rx_vec_sig, local_tx => local_tx_sig, local_vc_write_tx => local_vc_write_tx_sig, local_incr_tx_vec => local_incr_tx_vec_sig ); -- Clock generation process clk_process: process begin clk_tb <= '0'; wait for 5 ns; clk_tb <= '1'; wait for 5 ns; end process; -----------------------NoC connection has to be changed-------------------- -- local_noc_rx1 <= local_noc_tx2; -- local_noc_rx2 <= local_noc_tx1; --inst1 [rx_dma <= tx_noc] & [rx_noc <= tx_dma] source one[1] --rx local_rx_sig(1) <= local_tx_sig1; local_vc_write_rx_sig(4) <= local_vc_write_tx_sig1; --tx local_rx_sig1 <= local_tx_sig(1); local_vc_write_rx_sig1 <= local_vc_write_tx_sig(4); --inst2 [rx_dma <= tx_noc] & [rx_noc <= tx_dma] source zero[0] -- rx local_rx_sig(0) <= local_tx_sig2; local_vc_write_rx_sig(0) <= local_vc_write_tx_sig2; --tx destination one[1] local_rx_sig2 <= local_tx_sig(0); local_vc_write_rx_sig2 <= local_vc_write_tx_sig(0); -- Simulation process to assign values to CtrlCommand simproc: process begin cmd_valid <= '0'; rst_tb <= '0'; wait for 10 ns; rst_tb <= '1'; wait for 40 ns; -----------------------------------------------Test1--------------------------------------------------- cmd_inst_funct2 <= "0011110"; --#define DMA_WRITE_TO_RAM 30 /// 0X1E cmd_inst_funct1 <= "0011111"; --#define DMA_READ_FROM_RAM 31 /// 0X1F cmd_rs1_1 <= std_logic_vector(to_unsigned(0, 57)) & "0000010"; --7 bit address & 57 bit zeros cmd_rs1_2 <= std_logic_vector(to_unsigned(0, 57)) & "0001000"; --7 bit address & 57 bit zeros cmd_rs2_1 <= std_logic_vector(to_unsigned(0, 59)) & "00100"; --5 bit size & 59 bit zeros cmd_rs2_2 <= std_logic_vector(to_unsigned(0, 59)) & "00100"; --5 bit size & 59 bit zeros wait for 20 ns; cmd_valid <= '1'; wait for 40 ns; cmd_valid <= '0'; -- local_vc_write_tx_noc2 <= '1'; wait for 180 ns; -- local_vc_write_tx_noc2 <= '0'; for i in 0 to to_integer(unsigned(cmd_rs2_1)) loop if(ram_sig1(to_integer(unsigned(cmd_rs1_1)) + i ) /= ram_sig2(to_integer(unsigned(cmd_rs1_2)) + i)) then report "Test is failed: memory elements are not equal at location " & "cmd_rs1_1 = " & integer'image(to_integer(unsigned(cmd_rs1_1)+i)) & ", cmd_rs1_2 = " & integer'image(to_integer(unsigned(cmd_rs1_2)+i)) severity note; failed_status_test1 <= '1'; exit; -- Exit the loop end if; end loop; wait for 20 ns; -------------------------------------------------------------------------------------------------------------- if failed_status_test1 = '0' then report "Test is passed: memory elements are equal starting locations " & "cmd_rs1_1 = " & integer'image(to_integer(unsigned(cmd_rs1_1))) & ", cmd_rs1_2 = " & integer'image(to_integer(unsigned(cmd_rs1_2))) severity note; end if; wait for 1000 ns; -- -- wait for 1000 ns ; end process; end architecture;