201 lines
5.9 KiB
VHDL
201 lines
5.9 KiB
VHDL
-------------------------------------------------------------------------------
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-- Title : Test pattern generator
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-- Project : NoC testbench generator
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-------------------------------------------------------------------------------
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-- File : traffic_gen.vhd
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-- Author : Seyed Nima Omidsajedi <nima@omidsajedi.com>
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-- Company : University of Bremen
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-------------------------------------------------------------------------------
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-- Copyright (c) 2019
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-------------------------------------------------------------------------------
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-- Vesion : 1.9.0
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_textio.all;
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use std.textio.all;
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use work.NOC_3D_PACKAGE.all;
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entity traffic_gen is
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generic(
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flit_width : positive := flit_size;
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router_credit : integer := 4;
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srl_fifo_depth : integer := 8;
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inj_time_text : string := "injection_time.txt";
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packet_length_text : string := "packet_length.txt";
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image_2_flits_text : string := "data_header.txt";
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inj_time_2_noc_text : string := "inj_time_2_noc.txt"
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);
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port(
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clk, rst: in std_logic := '0';
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valid: out std_logic := '0';
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incr: in std_logic := '0';
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data_out: out flit := (others => '0')
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);
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end entity;
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architecture behave of traffic_gen is
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component srl_fifo is
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generic ( buffer_depth : integer := srl_fifo_depth );
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port(
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data_in : in flit;
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data_out : out flit;
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rst : in std_logic;
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write_en : in std_logic;
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read_en : in std_logic;
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buffer_full : out std_logic;
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buffer_empty : out std_logic;
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clk : in std_logic
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);
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end component;
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signal data_in : flit := (others => '0');
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signal data_out_rsl_fifo : flit;
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signal credit: integer := router_credit;
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signal valid_signal : std_logic := '0';
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signal temp_inj_time : natural;
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signal temp_packet_length : natural := 0;
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signal counter: natural := 0;
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signal write_en : std_logic := '0';
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signal buffer_full : std_logic := '0';
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signal buffer_empty : std_logic := '1';
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-- Used text files
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file inj_time : text open read_mode is inj_time_text;
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file packet_length : text open read_mode is packet_length_text;
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file image_2_flits : text open read_mode is image_2_flits_text;
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file inj_time_2_noc : text open write_mode is inj_time_2_noc_text;
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begin
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-------------------------------------------------------------------
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------------------ internal buffer component ----------------------
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int_buffer: entity work.srl_fifo
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generic map ( buffer_depth => srl_fifo_depth)
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port map (
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data_in => data_in,
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data_out => data_out_rsl_fifo,
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rst => rst,
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write_en => write_en,
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read_en => valid_signal,
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buffer_full => buffer_full,
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buffer_empty => buffer_empty,
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clk => clk);
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-------------------------------------------------------------------
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----------- Read text files into the internal buffer --------------
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read_packet_length: process
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variable input_line : line;
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variable next_data_packet_length: natural;
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variable next_inj_time: natural;
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variable next_data_flit: flit;
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begin
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wait until ((rst = not(RST_LVL)) and rising_edge(clk)); -- set reset for design
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while not (endfile(packet_length)) loop
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write_en <= '0';
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readline(packet_length, input_line);
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read(input_line, next_data_packet_length);
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temp_packet_length <= next_data_packet_length;
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readline(inj_time, input_line);
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read(input_line, next_inj_time);
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temp_inj_time <= next_inj_time;
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wait until (counter = temp_inj_time - 1) and rising_edge(clk);
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-- Send Data into internal Buffer
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for i in 0 to (temp_packet_length - 1) loop
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readline(image_2_flits, input_line);
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read(input_line, next_data_flit);
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data_in <= next_data_flit;
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write_en <= '1';
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wait until rising_edge(clk);
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end loop;
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end loop;
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-- Put zeros after the whole message tranmission
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if endfile(packet_length) then
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write_en <= '0';
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data_in <= (others => '0');
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end if;
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end process;
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-------------------------------------------------------------------
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------------------------- Clk counter -----------------------------
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clk_counter: process(clk)
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begin
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if (rising_edge(clk)) then
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if (rst = RST_LVL) then
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counter <= 0;
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else
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counter <= counter + 1;
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end if;
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end if;
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end process;
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-------------------------------------------------------------------
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------------------------ Credit counter ---------------------------
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credit_counter: process(clk, rst)
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begin
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if (rising_edge(clk)) then
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if (rst = RST_LVL) then
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credit <= router_credit ;
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else
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if ((credit > 0) and valid_signal = '1' and incr = '0') then
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credit <= credit - 1;
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elsif ((credit < router_credit) and valid_signal = '0') then
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credit <= credit + 1;
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end if;
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end if;
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end if;
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end process;
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-------------------------------------------------------------------
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---------------------- Determine valid flag -----------------------
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data_out <= data_out_rsl_fifo;
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valid_flag: process(buffer_empty, credit, incr)
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begin
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if ( buffer_empty = '0' and (( credit > 0) or (incr = '1'))) then
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valid <= '1';
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valid_signal <= '1';
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else
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valid <= '0';
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valid_signal <= '0';
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end if;
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end process;
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-------------------------------------------------------------------
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------------------- Save injection time to NoC --------------------
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write_inj_time: process(clk, rst)
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variable rowOut: line;
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variable data_time: time := 0 ns;
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begin
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if clk = '1' and clk'event and rst = not(RST_LVL) then
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if (valid_signal = '1') then
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data_time := now - clk_period;
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write(rowOut, data_time);
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writeline(inj_time_2_noc, rowOut);
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end if;
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end if;
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end process;
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--------------------------------------------------------------------
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-------------------------------------------------------------------
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end architecture;
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