160 lines
7.9 KiB
VHDL
160 lines
7.9 KiB
VHDL
-------------------------------------------------------------------------------
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-- Title : Virtual channel allocator
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-- Project : Modular, heterogenous 3D NoC
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-------------------------------------------------------------------------------
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-- File : vc_allocator.vhd
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-- Author : Lennart Bamberg <lennart@t440s>
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-- Company :
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-- Created : 2018-11-11
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-- Last update: 2018-11-28
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-- Platform :
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-- Standard : VHDL'93/02
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-------------------------------------------------------------------------------
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-- Description: New package are detected in an input port, then the required
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-- informations (routing & packet length) are decoded from the
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-- header. Finally, a suitable output virtual channel is assigned.
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-- COMMENT:
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-- Currently, this version is not used (but the high perf. one)!
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-------------------------------------------------------------------------------
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-- Copyright (c) 2018
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-------------------------------------------------------------------------------
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-- Revisions :
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-- Date Version Author Description
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-- 2018-11-11 1.0 lennart Created
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_misc.all;
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use work.NOC_3D_PACKAGE.all;
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use work.TURNS_3D_NOC.all;
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entity vc_allocator is
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generic (
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port_num : positive := 7;
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-- Integer range has to be / is (0 to port_num-1)
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port_exist : integer_vec := (0, 1, 2, 3, 4, 5, 6);
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Xis : natural := 1;
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Yis : natural := 1;
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Zis : natural := 1;
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header_incl_in_packet_length : boolean := true;
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rout_algo : string := "DXYU";
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vc_num_vec : integer_vec := (4 ,4 ,4 ,4 ,4 ,4 ,4 );
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vc_num_out_vec : integer_vec := (4 ,4 ,4 ,4 ,4 ,4 ,4 ));
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port (
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clk, rst : in std_logic;
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header : in header_inf_vector(int_vec_sum(vc_num_vec)-1 downto 0);
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enr_vc : in std_logic_vector(int_vec_sum(vc_num_vec)-1 downto 0);
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valid_data_vc_vec : in std_logic_vector(int_vec_sum(vc_num_vec)-1 downto 0);
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input_vc_in_use : out std_logic_vector(int_vec_sum(vc_num_vec)-1 downto 0);
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crossbar_ctrl_vec : out std_logic_vector(int_vec_sum(vc_num_out_vec)*
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bit_width(port_num-1)-1 downto 0);
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vc_sel_enc_vec : out vc_status_array_enc(int_vec_sum(vc_num_out_vec)-1 downto 0);
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output_vc_in_use : out std_logic_vector(int_vec_sum(vc_num_out_vec)-1 downto 0)
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);
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end entity vc_allocator;
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architecture rtl of vc_allocator is
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constant poss_routes : turn_table_3D := routes_3D(rout_algo);
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constant sel_width : positive := bit_width(port_num-1);
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signal ack_input : std_logic_vector(port_num-1 downto 0);
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signal packet_end : std_logic_vector(int_vec_sum(vc_num_vec)-1 downto 0);
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type rq_array is array (port_num-1 downto 0) of std_logic_vector(port_num-1 downto 0);
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type rq_array_filt is array (port_num-1 downto 0) of std_logic_vector(port_num-2 downto 0);
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signal granted_rq_array : rq_array;
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signal rq_vc_out_array : rq_array_filt;
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type vc_status_array_filt is array (port_num-1 downto 0) of vc_status_array(port_num-2 downto 0);
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signal packet_end_sort : vc_status_array_filt;
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signal granted_vc_sort : vc_status_array_filt;
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signal granted_vc : std_logic_vector(int_vec_sum(vc_num_vec)-1 downto 0);
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type ack_array_vc_out is array(port_num-1 downto 0) of std_logic_vector(port_num-2 downto 0);
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signal ack_rq_vc_out : ack_array_vc_out;
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begin -- architecture rtl
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GEN_PER_PORT : for i in 0 to port_num-1 generate
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constant ur_vc_in : natural := upper_range(vc_num_vec, i);
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constant lr_vc_in : natural := lower_range(vc_num_vec, i);
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constant ur_vc_out : natural := upper_range(vc_num_out_vec, i);
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constant lr_vc_out : natural := lower_range(vc_num_out_vec, i);
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begin
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---------------------------------------------------------------------------
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-- Header decoder and input arbiter per port-------------------------------
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---------------------------------------------------------------------------
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input_first_arbiter_i : entity work.header_arbiter_and_decoder
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generic map (
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Xis => Xis,
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Yis => Yis,
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Zis => Zis,
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port_num => port_num,
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port_exist => port_exist,
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port_is => port_exist(i),
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vc_num => vc_num_vec(i),
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header_incl_in_packet_length => header_incl_in_packet_length,
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rout_algo => rout_algo)
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port map (
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clk => clk,
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rst => rst,
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valid_data_vc => valid_data_vc_vec(ur_vc_in downto lr_vc_in),
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header => header(ur_vc_in downto lr_vc_in),
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enr_vc => enr_vc(ur_vc_in downto lr_vc_in),
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ack_vc => ack_input(i),
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granted_rq => granted_rq_array(i),
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input_vc_in_use => input_vc_in_use(ur_vc_in downto lr_vc_in),
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packet_end => packet_end(ur_vc_in downto lr_vc_in),
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granted_vc => granted_vc(ur_vc_in downto lr_vc_in));
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---------------------------------------------------------------------------
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-- Output VC arbiter/allocator per port -----------------------------------
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---------------------------------------------------------------------------
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output_last_arbiter_i : entity work.vc_output_allocator
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generic map (
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port_num => port_num,
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vc_num_out => vc_num_out_vec(i))
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port map (
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clk => clk,
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rst => rst,
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rq_vc_out => rq_vc_out_array(i),
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granted_vc => granted_vc_sort(i),
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packet_end => packet_end_sort(i),
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crossbar_ctrl_vec => crossbar_ctrl_vec((ur_vc_out+1)*sel_width-1 downto lr_vc_out*sel_width),
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vc_sel_enc => vc_sel_enc_vec(ur_vc_out downto lr_vc_out),
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output_vc_in_use => output_vc_in_use(ur_vc_out downto lr_vc_out),
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ack_rq_vc_out => ack_rq_vc_out(i)
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);
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end generate;
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-----------------------------------------------------------------------------
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-- Clock Wise Wiring --------------------------------------------------------
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-----------------------------------------------------------------------------
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WIRING_INAR_TO_OUTAR : process(ack_rq_vc_out, granted_rq_array, granted_vc,
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packet_end)
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variable var_in : natural;
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variable ack_rq_vc_out_var : std_logic_vector(port_num-1 downto 0);
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begin
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rq_vc_out_array <= (others => (others => '0'));
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granted_vc_sort <= (others => (others => (others => '0')));
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packet_end_sort <= (others => (others => (others => '0')));
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ack_rq_vc_out_var := (others => '0');
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for y in 0 to port_num-1 loop -- For the VC-out allocator y,
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for x in 0 to port_num-2 loop -- the X^th input is
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if y+x < port_num-1 then
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var_in := y+x+1;
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else -- Modulo (start from beginning)
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var_in := y+x-port_num+1;
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end if;
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if poss_routes(port_exist(var_in))(port_exist(y)) then
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rq_vc_out_array(y)(x) <= granted_rq_array(var_in)(y);
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granted_vc_sort(y)(x)(vc_num_vec(var_in)-1 downto 0)
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<= slice(granted_vc, vc_num_vec, var_in);
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packet_end_sort(y)(x)(vc_num_vec(var_in)-1 downto 0)
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<= slice(packet_end, vc_num_vec, var_in);
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ack_rq_vc_out_var(var_in) := ack_rq_vc_out_var(var_in) or
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ack_rq_vc_out(y)(x); --feedback ack
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end if;
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end loop;
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end loop;
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ack_input <= ack_rq_vc_out_var;
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end process;
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end architecture rtl;
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