kkoloth
91dbf4503c
Implementation of the DMA logic up to 2/12/24. [Note: Testbench creation and full_DMA signal mapping is pending]
51 lines
No EOL
2.2 KiB
VHDL
51 lines
No EOL
2.2 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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----------------------RAM Entity---------------------------
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entity Single_Port_RAM is
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port(
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clk : in std_logic;
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rst : in std_logic;
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Address_bus : in std_logic_vector(7 downto 0); --From DMA
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Read_write_Enable : in std_logic_vector(1 downto 0); --From DMA
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Data_bus_in : in std_logic_vector(7 downto 0); --From Noc
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Data_bus_out : out std_logic_vector(7 downto 0) --From Noc
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);
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end entity;
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----------------------RAM Behaviour------------------------
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architecture Single_Port_RAM_behav of Single_Port_RAM is
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------- define the new type for the 128x8 RAM
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type RAM_ARRAY is array (0 to 127 ) of std_logic_vector (7 downto 0);
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-------- initial values in the RAM to X00
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signal RAM: RAM_ARRAY := (others=>x"00");
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signal initialized : std_logic; -- Initialization flag
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begin
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process(clk, rst)
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begin
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if rst = '0' then -- inverted reset
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Data_bus_out <= (others => '0');
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initialized <= '1';
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elsif rising_edge(clk) then
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--Setting value to the RAM to coresponding index
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if initialized = '1' then
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for i in 0 to 127 loop
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RAM(i) <= std_logic_vector(to_unsigned(i,8));
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end loop;
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initialized <= '0';
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end if;
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--Read Write functionality of RAM
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if (Read_write_Enable(0) = '0' and Read_write_Enable(1) = '1' )then --read enable; [MSB] READ Enable [LSB] WRITE Enable
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Data_bus_out <= RAM(to_integer(unsigned(Address_bus(6 downto 0 )))); -- read data from RAM
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elsif (Read_write_Enable(0) = '1' and Read_write_Enable(1) = '0') then --write enable; [MSB] READ Enable [LSB] WRITE Enable
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RAM(to_integer(unsigned(Address_bus(6 downto 0)))) <= Data_bus_in(7 downto 0); -- Write data to RAM
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Data_bus_out <= (others => '0');
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else
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Data_bus_out <= (others => '0');
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end if;
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end if;
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end process;
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end architecture; |