60 lines
No EOL
2.8 KiB
VHDL
60 lines
No EOL
2.8 KiB
VHDL
library ieee;
|
|
use ieee.std_logic_1164.all;
|
|
use ieee.numeric_std.all;
|
|
|
|
----------------------RAM Entity---------------------------
|
|
entity Single_Port_RAM is
|
|
generic (
|
|
DATA_SIZE : integer := 7; -- Default source ID should be changed
|
|
ADDRESS_SIZE : integer := 6 -- Default destination ID should be changed
|
|
);
|
|
--constant DATA_SIZE : integer := 7; -- Define constant for vector size for data of 8 bits
|
|
--constant ADDRESS_SIZE : integer := 6; -- Define constant for vector size for address 7 bits
|
|
port(
|
|
clk : in std_logic;
|
|
rst : in std_logic;
|
|
Address_bus : in std_logic_vector(ADDRESS_SIZE downto 0); -- From DMA
|
|
Read_Enable : in std_logic; -- From DMA
|
|
Write_Enable : in std_logic; -- From DMA
|
|
Data_bus_in : in std_logic_vector(DATA_SIZE downto 0); -- From NoC
|
|
Data_bus_out : out std_logic_vector(DATA_SIZE downto 0) -- From NoC
|
|
);
|
|
end entity;
|
|
|
|
----------------------RAM Behaviour------------------------
|
|
architecture Single_Port_RAM_behav of Single_Port_RAM is
|
|
|
|
------- define the new type for the 128x8 RAM
|
|
type RAM_ARRAY is array (0 to 127 ) of std_logic_vector (DATA_SIZE downto 0);
|
|
-------- initial values in the RAM to X00
|
|
signal RAM: RAM_ARRAY := (others=>x"00");
|
|
signal initialized : std_logic; -- Initialization flag
|
|
|
|
begin
|
|
process(clk, rst)
|
|
begin
|
|
if rst = '0' then -- inverted reset
|
|
Data_bus_out <= (others => '0');
|
|
initialized <= '1';
|
|
elsif rising_edge(clk) then
|
|
--Setting value to the RAM to coresponding index_testing purpouse
|
|
-- synthesis translate_off
|
|
if initialized = '1' then
|
|
for i in 0 to 127 loop
|
|
RAM(i) <= std_logic_vector(to_unsigned(i,8));
|
|
end loop;
|
|
initialized <= '0';
|
|
end if;
|
|
-- synthesis translate_on
|
|
--Read Write functionality of RAM
|
|
if (Read_Enable = '1' and Write_Enable = '0' )then --read enable; [MSB] READ Enable [LSB] WRITE Enable
|
|
Data_bus_out <= RAM(to_integer(unsigned(Address_bus(ADDRESS_SIZE downto 0 )))); -- read data from RAM
|
|
elsif (Read_Enable = '0' and Write_Enable = '1') then --write enable; [MSB] READ Enable [LSB] WRITE Enable
|
|
RAM(to_integer(unsigned(Address_bus(ADDRESS_SIZE downto 0)))) <= Data_bus_in(DATA_SIZE downto 0); -- Write data to RAM
|
|
Data_bus_out <= (others => '0');
|
|
else
|
|
Data_bus_out <= (others => '0');
|
|
end if;
|
|
end if;
|
|
end process;
|
|
end architecture; |