319 lines
17 KiB
VHDL
319 lines
17 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.NOC_3D_PACKAGE.all;
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-- vcom -work work -2008 -explicit -stats=none D:/project_item_ids/DMA_VHDL/DMA_ARCH_MODULAR_DESGIN/FULL_DMA_tb.vhd
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---vsim -gui work.fulldmatb
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entity fulldmatb is
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end entity;
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architecture fulldmatb_arch of fulldmatb is
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constant DATA_SIZE : natural := 7; -- Define constant for vector size for data of 8 bits
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constant INST_SIZE : natural := 6; -- Define constant for vector size for inst of 6 bits
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constant LENGTH : natural := 4; -- Define constant for vector size for size of Id's 5 bits
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constant PACKET : natural := 31; -- Define constant for vector size for size of packet 32 bits
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constant REG_SIZE : natural := 63; -- Define constant for vector size for size of Reg 64 bits
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constant DMA_WRITE_TO_RAM : std_logic_vector(6 downto 0) := std_logic_vector(to_unsigned(15, 7)); --"0001111";
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constant DMA_READ_TO_RAM : std_logic_vector(6 downto 0) := std_logic_vector(to_unsigned(127, 7)); --"1111111";
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-- constant SOURCE_ID_int1 : integer := 1;
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-- constant DEST_ID_int1 : integer := 0;
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-- constant SOURCE_ID_int2 : integer := 0;
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-- constant DEST_ID_int2 : integer := 1;
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---- type flit_vector is array (natural range <>) of std_logic_vector(31 downto 0);
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component full_dma is
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generic (
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DATA_SIZE : natural := 7; -- Define constant for vector size for data of 8 bits
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INST_SIZE : natural := 6; -- Define constant for vector size for inst of 6 bits
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LENGTH : natural := 4; -- Define constant for vector size for size of Id's 5 bits
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PACKET : natural := 31; -- Define constant for vector size for size of packet 32 bits
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REG_SIZE : natural := 63; -- Define constant for vector size for size of Reg 64 bits
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SOURCE_ID_NEW : std_logic_vector(5 downto 0) := "000000"; -- Default source ID should be changed
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DEST_ID_NEW : std_logic_vector(5 downto 0) := "000001" -- Default destination ID should be changed
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);
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port(
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clk : in std_logic;
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rst : in std_logic;
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local_noc_rx : in std_logic_vector(PACKET downto 0);--- --From Noc
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local_vc_write_rx_noc : in std_logic; ---_vector(192-1 downto 0);--From NoC
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local_incr_rx_vec_noc : in std_logic;
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cmd_valid : in std_logic; --From Core
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cmd_inst_funct : in std_logic_vector(INST_SIZE downto 0); --From Core
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cmd_inst_opcode : in std_logic_vector(INST_SIZE downto 0); --From Core
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cmd_inst_rd : in std_logic_vector(LENGTH downto 0); --From Core
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cmd_inst_rs1 : in std_logic_vector(LENGTH downto 0); --From Core
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cmd_inst_rs2 : in std_logic_vector(LENGTH downto 0); --From Core
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cmd_inst_xd : in std_logic; --From Core
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cmd_inst_xs1 : in std_logic; --From Core
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cmd_inst_xs2 : in std_logic; --From Core
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cmd_rs1 : in std_logic_vector(REG_SIZE downto 0); --From Core
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cmd_rs2 : in std_logic_vector(REG_SIZE downto 0); --From Core
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cmd_busy : out std_logic; --To Core
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cmd_ready : out std_logic; --To Core --always one
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local_noc_tx : out std_logic_vector(PACKET downto 0);--- --To NoC
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local_vc_write_tx_noc : out std_logic; ---_vector(192-1 downto 0);--To NoC
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local_incr_tx_vec_noc : out std_logic --To NoC
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);
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end component;
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component full_noc is
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port(
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clk, rst : in std_logic;
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local_rx : in flit_vector(48-1 downto 0);
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local_vc_write_rx : in std_logic_vector(192-1 downto 0);
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local_incr_rx_vec : in std_logic_vector(192-1 downto 0);
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local_tx : out flit_vector(48-1 downto 0);
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local_vc_write_tx : out std_logic_vector(192-1 downto 0);
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local_incr_tx_vec : out std_logic_vector(192-1 downto 0)
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);
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end component;
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signal clk_tb : std_logic;
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signal rst_tb : std_logic;
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signal local_rx_sig : flit_vector(48-1 downto 0) := (others => (others => '0')); --map coressponding flit to port
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signal local_tx_sig : flit_vector(48-1 downto 0) := (others => (others => '0'));
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signal local_vc_write_rx_sig : std_logic_vector(192-1 downto 0) := (others => '0');
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signal local_incr_rx_vec_sig : std_logic_vector(192-1 downto 0) := (others => '0');
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signal local_vc_write_tx_sig : std_logic_vector(192-1 downto 0) := (others => '0');
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signal local_incr_tx_vec_sig : std_logic_vector(192-1 downto 0) := (others => '0');
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signal local_vc_write_tx_noc1 : std_logic;
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signal cmd_valid,local_vc_write_tx_noc2 : std_logic;
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signal cmd_inst_funct1,cmd_inst_funct2 : std_logic_vector(INST_SIZE downto 0);
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signal cmd_inst_opcode : std_logic_vector(INST_SIZE downto 0);
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signal cmd_inst_rd : std_logic_vector(LENGTH downto 0);
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signal cmd_inst_rs1 : std_logic_vector(LENGTH downto 0);
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signal cmd_inst_rs2 : std_logic_vector(LENGTH downto 0);
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signal cmd_inst_xd : std_logic;
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signal cmd_inst_xs1 : std_logic;
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signal cmd_inst_xs2 : std_logic;
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signal cmd_rs1_1, cmd_rs1_2 : std_logic_vector(REG_SIZE downto 0);
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signal cmd_rs2_1, cmd_rs2_2 : std_logic_vector(REG_SIZE downto 0);
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signal cmd_busy : std_logic;
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signal cmd_ready : std_logic;
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signal local_tx_sig1, local_tx_sig2 : std_logic_vector(PACKET downto 0);--- --To NoC
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signal local_rx_sig1, local_rx_sig2 : std_logic_vector(PACKET downto 0);--- --To NoC
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signal local_vc_write_rx_sig1, local_vc_write_rx_sig2 : std_logic;
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signal local_vc_write_tx_sig1, local_vc_write_tx_sig2 : std_logic;
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signal local_incr_tx_vec_sig1, local_incr_tx_vec_sig2 : std_logic;
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signal local_incr_rx_vec_sig1, local_incr_rx_vec_sig2 : std_logic;
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signal failed_status_test1 : std_logic := '0';
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type ram_array is array (0 to 127 ) of std_logic_vector (DATA_SIZE downto 0);
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alias ram_sig1 is <<signal.fulldma_inst1.single_port_ram_inst.ram: ram_array>>;
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alias ram_sig2 is <<signal.fulldma_inst2.single_port_ram_inst.ram: ram_array>>;
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-- alias ram_sig1 is fulldma_inst1.single_port_ram_inst.ram : ram_array;
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begin
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-- Component instantiation with a label
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fulldma_inst1 : full_dma
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generic map (
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SOURCE_ID_NEW => "000001", -- Set source ID
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DEST_ID_NEW => "000000" -- Set destination ID
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)
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port map (
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clk => clk_tb,
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rst => rst_tb,
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-- local_incr_tx_vec_noc => local_incr_tx_vec_sig(1 sll (DEST_ID_inst1 + 1)),
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-- local_noc_rx => local_rx_sig(DEST_ID_inst1),
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-- local_vc_write_tx_noc => local_vc_write_tx_sig(1 sll (DEST_ID_inst1 + 1)),
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local_noc_rx => local_rx_sig1,
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local_vc_write_rx_noc => local_vc_write_rx_sig1,
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local_incr_rx_vec_noc => local_incr_rx_vec_sig1,
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cmd_valid => cmd_valid,
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cmd_inst_funct => cmd_inst_funct1,
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cmd_inst_opcode => cmd_inst_opcode,
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cmd_inst_rd => cmd_inst_rd,
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cmd_inst_rs1 => cmd_inst_rs1,
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cmd_inst_rs2 => cmd_inst_rs2,
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cmd_inst_xd => cmd_inst_xd,
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cmd_inst_xs1 => cmd_inst_xs1,
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cmd_inst_xs2 => cmd_inst_xs2,
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cmd_rs1 => cmd_rs1_1,
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cmd_rs2 => cmd_rs2_1,
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cmd_busy => cmd_busy,
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cmd_ready => cmd_ready,
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local_noc_tx => local_tx_sig1,
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local_vc_write_tx_noc => local_vc_write_tx_sig1,
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local_incr_tx_vec_noc => local_incr_tx_vec_sig1
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-- local_incr_rx_vec_noc => local_incr_tx_vec_sig(1 sll (SOURCE_ID_inst1 + 1)),
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-- local_noc_tx => local_tx_sig(SOURCE_ID_inst1),
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-- local_vc_write_rx_noc => local_vc_write_tx_sig(1 sll (SOURCE_ID_inst1 + 1))
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);
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-- Component instantiation with a label
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fulldma_inst2 : full_dma
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generic map (
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SOURCE_ID_NEW => "000000", -- Set source ID
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DEST_ID_NEW => "000001" -- Set destination ID
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)
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port map (
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clk => clk_tb,
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rst => rst_tb,
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-- local_incr_tx_vec_noc => local_incr_tx_vec_sig(1 sll (DEST_ID_inst2 + 1)),
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-- local_noc_rx => local_rx_sig(DEST_ID_inst2),
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-- local_vc_write_tx_noc => local_vc_write_tx_sig(1 sll (DEST_ID_inst2 + 1)),
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local_noc_rx => local_rx_sig2,
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local_vc_write_rx_noc => local_vc_write_rx_sig2,
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local_incr_rx_vec_noc => local_incr_rx_vec_sig2,
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cmd_valid => cmd_valid,
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cmd_inst_funct => cmd_inst_funct2,
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cmd_inst_opcode => cmd_inst_opcode,
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cmd_inst_rd => cmd_inst_rd,
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cmd_inst_rs1 => cmd_inst_rs1,
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cmd_inst_rs2 => cmd_inst_rs2,
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cmd_inst_xd => cmd_inst_xd,
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cmd_inst_xs1 => cmd_inst_xs1,
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cmd_inst_xs2 => cmd_inst_xs2,
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cmd_rs1 => cmd_rs1_2,
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cmd_rs2 => cmd_rs2_2,
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cmd_busy => cmd_busy,
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cmd_ready => cmd_ready,
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local_noc_tx => local_tx_sig2,
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local_vc_write_tx_noc => local_vc_write_tx_sig2,
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local_incr_tx_vec_noc => local_incr_tx_vec_sig2
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-- local_incr_rx_vec_noc => local_incr_tx_vec_sig(1 sll (SOURCE_ID_inst2 + 1)),
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-- local_noc_tx => local_tx_sig(SOURCE_ID_inst2),
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-- local_vc_write_rx_noc => local_vc_write_tx_sig(1 sll (SOURCE_ID_inst2 + 1))
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);
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full_noc_inst1 : full_noc
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port map(
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clk => clk_tb,
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rst => rst_tb,
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local_rx => local_rx_sig,
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local_vc_write_rx => local_vc_write_rx_sig,
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local_incr_rx_vec => local_incr_rx_vec_sig,
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local_tx => local_tx_sig,
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local_vc_write_tx => local_vc_write_tx_sig,
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local_incr_tx_vec => local_incr_tx_vec_sig
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);
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-- Clock generation process
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clk_process: process
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begin
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clk_tb <= '0'; wait for 5 ns;
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clk_tb <= '1'; wait for 5 ns;
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end process;
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-----------------------NoC connection has to be changed--------------------
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-- local_noc_rx1 <= local_noc_tx2;
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-- local_noc_rx2 <= local_noc_tx1;
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--inst1 [rx_dma <= tx_noc] & [rx_noc <= tx_dma] source one[1]
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--rx
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local_rx_sig(1) <= local_tx_sig1;
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local_vc_write_rx_sig(4) <= local_vc_write_tx_sig1;
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--local_incr_rx_vec_sig(0) <= local_incr_tx_vec_sig1;
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--tx
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local_rx_sig1 <= local_tx_sig(1);
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local_vc_write_rx_sig1 <= local_vc_write_tx_sig(4);
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--local_incr_rx_vec_sig1 <= local_incr_tx_vec_sig(4);
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--inst2 [rx_dma <= tx_noc] & [rx_noc <= tx_dma] source zero[0]
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-- rx
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local_rx_sig(0) <= local_tx_sig2;
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local_vc_write_rx_sig(0) <= local_vc_write_tx_sig2;
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--local_incr_rx_vec_sig(4) <= local_incr_tx_vec_sig2;
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--tx destination one[1]
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local_rx_sig2 <= local_tx_sig(0);
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local_vc_write_rx_sig2 <= local_vc_write_tx_sig(0);
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--local_incr_rx_vec_sig2 <= local_incr_tx_vec_sig(0);
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-- Simulation process to assign values to CtrlCommand
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simproc: process
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begin
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-- local_vc_write_tx_noc2 <= '0';
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cmd_valid <= '0';
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rst_tb <= '0';
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wait for 10 ns;
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rst_tb <= '1';
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wait for 40 ns;
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-----------------------------------------------Test1---------------------------------------------------
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-- cmd_inst_funct2 <= std_logic_vector(to_unsigned(15, 7)); -- --#define DMA_WRITE_TO_RAM 30 /// 0X1E
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-- cmd_inst_funct1 <= std_logic_vector(to_unsigned(127, 7)); -- --#define DMA_READ_FROM_RAM 31 /// 0X1F
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cmd_inst_funct2 <= "0011110"; --#define DMA_WRITE_TO_RAM 30 /// 0X1E
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cmd_inst_funct1 <= "0011111"; --#define DMA_READ_FROM_RAM 31 /// 0X1F
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cmd_rs1_1 <= std_logic_vector(to_unsigned(0, 57)) & "0000010"; --7 bit address & 57 bit zeros
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cmd_rs1_2 <= std_logic_vector(to_unsigned(0, 57)) & "0001000"; --7 bit address & 57 bit zeros
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cmd_rs2_1 <= std_logic_vector(to_unsigned(0, 59)) & "00100"; --5 bit size & 59 bit zeros
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cmd_rs2_2 <= std_logic_vector(to_unsigned(0, 59)) & "00100"; --5 bit size & 59 bit zeros
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wait for 20 ns;
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cmd_valid <= '1';
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wait for 40 ns;
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cmd_valid <= '0';
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-- local_vc_write_tx_noc2 <= '1';
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wait for 180 ns;
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-- local_vc_write_tx_noc2 <= '0';
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for i in 0 to to_integer(unsigned(cmd_rs2_1)) loop
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if(ram_sig1(to_integer(unsigned(cmd_rs1_1)) + i ) /= ram_sig2(to_integer(unsigned(cmd_rs1_2)) + i)) then
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report "Test is failed: memory elements are not equal at location " &
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"cmd_rs1_1 = " & integer'image(to_integer(unsigned(cmd_rs1_1)+i)) &
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", cmd_rs1_2 = " & integer'image(to_integer(unsigned(cmd_rs1_2)+i))
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severity note;
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failed_status_test1 <= '1';
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exit; -- Exit the loop
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end if;
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end loop;
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wait for 20 ns;
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----------------------------------------------Test2------------------------------------------------------
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-- cmd_inst_funct2 <= std_logic_vector(to_unsigned(15, 7)); -- --#define DMA_WRITE_TO_RAM 30 /// 0X1E
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-- cmd_inst_funct1 <= std_logic_vector(to_unsigned(127, 7)); -- --#define DMA_READ_FROM_RAM 31 /// 0X1F
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cmd_inst_funct1 <= "0011110"; --#define DMA_WRITE_TO_RAM 30 /// 0X1E
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cmd_inst_funct2 <= "0011111"; --#define DMA_READ_FROM_RAM 31 /// 0X1F
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cmd_rs1_2 <= std_logic_vector(to_unsigned(0, 57)) & "0000010"; --7 bit address & 57 bit zeros
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cmd_rs1_1 <= std_logic_vector(to_unsigned(0, 57)) & "0001000"; --7 bit address & 57 bit zeros
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cmd_rs2_2 <= std_logic_vector(to_unsigned(0, 59)) & "00100"; --5 bit size & 59 bit zeros
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cmd_rs2_1 <= std_logic_vector(to_unsigned(0, 59)) & "00100"; --5 bit size & 59 bit zeros
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wait for 20 ns;
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cmd_valid <= '1';
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wait for 40 ns;
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cmd_valid <= '0';
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-- local_vc_write_tx_noc2 <= '1';
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wait for 180 ns;
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-- local_vc_write_tx_noc2 <= '0';
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for i in 0 to to_integer(unsigned(cmd_rs2_1)) loop
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if(ram_sig1(to_integer(unsigned(cmd_rs1_1)) + i ) /= ram_sig2(to_integer(unsigned(cmd_rs1_2)) + i)) then
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report "Test is failed: memory elements are not equal at location " &
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"cmd_rs1_1 = " & integer'image(to_integer(unsigned(cmd_rs1_1)+i)) &
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", cmd_rs1_2 = " & integer'image(to_integer(unsigned(cmd_rs1_2)+i))
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severity note;
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failed_status_test1 <= '1';
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exit; -- Exit the loop
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end if;
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end loop;
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wait for 20 ns;
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--------------------------------------------------------------------------------------------------------------
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if failed_status_test1 = '0' then
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report "Test is passed: memory elements are equal starting locations " &
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"cmd_rs1_1 = " & integer'image(to_integer(unsigned(cmd_rs1_1))) &
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", cmd_rs1_2 = " & integer'image(to_integer(unsigned(cmd_rs1_2)))
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severity note;
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end if;
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wait for 1000 ns;
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-- -- wait for 1000 ns ;
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end process;
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end architecture;
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