133 lines
7.4 KiB
VHDL
133 lines
7.4 KiB
VHDL
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-- Header structure:
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-----------------------------------------------------------------------------------------------------
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--| | | 2bit | 2bit | 2bit | 2bit | 2bit | 2bit | |
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--| Flit_padding | Packet_id | Z_src | Y_src | X_src | Z_dest | Y_dest | X_dest | Packet_length |
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--|31 3bits 29|28 12 bits 17|16 6bits 11|10 6bits 5|4 5bits 0|
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-----------------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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----------------------NoC Interface Entity---------------------------
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entity noc_interface is
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-- constant DATA_SIZE : integer := 7; -- Define constant for vector size for data of 8 bits
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-- constant LENGTH : integer := 4; -- Define constant for vector size for size of Id's 5 bits
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-- constant PACKET : integer := 11; -- Define constant for vector size for size of Id's 12 bits
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-- constant REG_SIZE : integer := 31; -- Define constant for vector size for size of Reg 31 bits
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generic (
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DATA_SIZE : natural := 7; -- Define constant for vector size for data of 8 bits
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LENGTH : natural := 4; -- Define constant for vector size for size of Id's 5 bits
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PACKET : natural := 11; -- Define constant for vector size for size of Id's 12 bits
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REG_SIZE : natural := 31; -- Define constant for vector size for size of Reg 31 bits
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SOURCE_ID : std_logic_vector(5 downto 0) := "000000"; -- Default source ID should be changed
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DEST_ID : std_logic_vector(5 downto 0) := "000001" -- Default destination ID should be changed
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);
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port(
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clk : in std_logic;
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rst : in std_logic;
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sent_valid_from_dma : in std_logic; --From DMA
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data_bus_noc_in : in std_logic_vector(DATA_SIZE downto 0); --From RAM
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tx_packet_length_noc : in std_logic_vector(LENGTH downto 0); --From DMA
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local_noc_rx : in std_logic_vector(REG_SIZE downto 0);--- --From Noc
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local_vc_write_rx_noc: in std_logic; ---_vector(192-1 downto 0); --From NoC
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local_incr_rx_vec_noc: in std_logic; --From NoC
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rx_packet_length_noc : out std_logic_vector(LENGTH downto 0); --To DMA
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local_noc_tx : out std_logic_vector(REG_SIZE downto 0);--- --To NoC
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local_vc_write_tx_noc: out std_logic; ---_vector(192-1 downto 0); --To NoC
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local_incr_tx_vec_noc: out std_logic; --To NoC
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receive_valid_to_dma : out std_logic; --To DMA
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sent_ack_to_dma : out std_logic_vector(LENGTH downto 0);--------- --To DMA
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data_bus_noc_out : out std_logic_vector(DATA_SIZE downto 0) --To RAM
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);
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end entity;
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----------------------NoC Interface Behaviour------------------------
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architecture noc_interface_arch of noc_interface is
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Signal packet_id : std_logic_vector(PACKET downto 0);
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signal count : std_logic_vector(LENGTH downto 0);
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signal sent_packet : std_logic_vector(LENGTH downto 0);
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signal packet_len : std_logic_vector(LENGTH downto 0);
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--signal packet_length : std_logic_vector(4 downto 0);
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begin
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rxprocess : process(clk, rst)
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begin
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if rst = '0' then
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rx_packet_length_noc <= (others => '0');
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local_noc_tx <= (others => '0');
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local_vc_write_tx_noc <= '0';
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--local_incr_tx_vec_noc <= '0';
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receive_valid_to_dma <= '0';
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sent_ack_to_dma <= (others => '0');
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data_bus_noc_out <= (others => '0');
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count <= (others => '0');
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sent_packet <= (others => '0');
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packet_id <= (others => '0');
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packet_len <= (others => '0');
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elsif rising_edge(clk) then
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--------------------Reading from NoC--------------------------------
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if (local_vc_write_rx_noc = '1') then
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if (local_noc_rx(31 downto 29) = "100") then
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rx_packet_length_noc <= local_noc_rx(LENGTH downto 0 ); --packet length
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packet_len <= local_noc_rx(LENGTH downto 0 ); --packet length
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count <= (others => '0'); --counter reset
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packet_id <= local_noc_rx(28 downto 17); --current packetid
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receive_valid_to_dma <= '1';
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elsif(unsigned(count) <= unsigned(packet_len) and unsigned(packet_len) > 0) then
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report "receive_valid_to_dma is 1 from Line 80";
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receive_valid_to_dma <= '1'; --valid to DMA
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count <= std_logic_vector(unsigned(count) + 1); --counter update
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data_bus_noc_out <= local_noc_rx(DATA_SIZE downto 0 ); --NoC is given to RAM
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else
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report "receive_valid_to_dma is 0 from Line 86";
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packet_len <= (others=>'0');
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receive_valid_to_dma <= '0';
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data_bus_noc_out <= (others=>'0');
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count <= (others=>'0');
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end if;
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--------------------Writing to NoC----------------------------------
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elsif ((sent_valid_from_dma = '1') and (to_integer(unsigned(tx_packet_length_noc)) >= 0)) then -- the valid from dma is one cycle behind
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if(sent_packet = "00000") then
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--sent_ack_to_dma <= std_logic_vector(unsigned(sent_packet) + 1); --to DMA updated value
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sent_packet <= std_logic_vector(unsigned(sent_packet) + 1);
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--updating packet id
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local_noc_tx <= "100" & packet_id & SOURCE_ID & DEST_ID & tx_packet_length_noc;
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local_vc_write_tx_noc <= '1';
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else
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sent_ack_to_dma <= sent_packet;--std_logic_vector(unsigned(sent_packet) + 1); --to DMA updated value
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sent_packet <= std_logic_vector(unsigned(sent_packet) + 1);
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local_noc_tx <= std_logic_vector(to_unsigned(0, 24)) & data_bus_noc_in; --24bit zeros in msb and 8 bit data
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local_vc_write_tx_noc <= '1';
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end if;
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else
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rx_packet_length_noc <= (others => '0');
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local_noc_tx <= (others => '0');
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local_vc_write_tx_noc <= '0';
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---local_incr_tx_vec_noc <= '0';
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receive_valid_to_dma <= '0';
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sent_ack_to_dma <= (others => '0');
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data_bus_noc_out <= (others => '0');
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count <= (others => '0');
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sent_packet <= (others => '0');
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end if;
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end if;
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end process;
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end architecture;
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