114 lines
5.2 KiB
VHDL
114 lines
5.2 KiB
VHDL
-------------------------------------------------------------------------------
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-- Title : Centralized arbiter
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-- Project : Modular, heterogenous 3D NoC
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-------------------------------------------------------------------------------
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-- File : arbiter.vhd
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-- Author : Lennart Bamberg <bamberg@office.item.uni-bremen.de>
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-- Company :
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-- Created : 2018-11-28
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-- Last update: 2018-11-28
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-- Platform :
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-- Standard : VHDL'93/02
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-------------------------------------------------------------------------------
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-- Description: Centralized arbiter, made up of an virtual channel and an switch
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-- allocator. Poss routes are exploited to heavily reduce compl.
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-------------------------------------------------------------------------------
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-- Copyright (c) 2018
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-------------------------------------------------------------------------------
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-- Revisions :
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-- Date Version Author Description
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-- 2018-11-28 1.0 bamberg Created
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.NOC_3D_PACKAGE.all;
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entity arbiter is
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generic (
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port_num : positive := 7;
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-- Integer range has to be / is (0 to port_num-1)
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port_exist : integer_vec := (0, 1, 2, 3, 4, 5, 6);
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Xis : natural := 1;
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Yis : natural := 1;
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Zis : natural := 1;
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header_incl_in_packet_length : boolean := true;
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rout_algo : string := "XYZ_ref";
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vc_num_vec : integer_vec := (4 ,4 ,4 ,4 ,4 ,4 ,4 );
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vc_num_out_vec : integer_vec := (4 ,4 ,4 ,4 ,4 ,4 ,4 );
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-- integer vector of range "0 to port_num-1, 0 to max_vc_num-1"
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vc_depth_array : vc_prop_int_array := ((4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) );
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vc_depth_out_array : vc_prop_int_array := ((4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) )
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);
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port (
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clk, rst : in std_logic;
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header : in header_inf_vector(int_vec_sum(vc_num_vec)-1 downto 0);
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valid_data_vc_vec : in std_logic_vector(int_vec_sum(vc_num_vec)-1 downto 0);
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incr_rx_vec : in std_logic_vector(int_vec_sum(vc_num_out_vec)-1 downto 0);
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crossbar_ctrl : out std_logic_vector(port_num*bit_width(port_num-1)-1 downto 0);
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vc_transfer_vec : out std_logic_vector(int_vec_sum(vc_num_vec)-1 downto 0);
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vc_write_tx_vec : out std_logic_vector(int_vec_sum(vc_num_out_vec)-1 downto 0));
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end entity arbiter;
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architecture structural of arbiter is
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signal vc_transfer_vec_int : std_logic_vector(int_vec_sum(vc_num_vec)-1 downto 0);
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signal input_vc_in_use : std_logic_vector(int_vec_sum(vc_num_vec)-1 downto 0);
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signal crossbar_ctrl_vec : std_logic_vector(int_vec_sum(vc_num_out_vec)*
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bit_width(port_num-1)-1 downto 0);
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signal output_vc_in_use : std_logic_vector(int_vec_sum(vc_num_out_vec)-1 downto 0);
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signal vc_sel_enc_vec : vc_status_array_enc(int_vec_sum(vc_num_out_vec)-1 downto 0);
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begin -- architecture structural
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--vc_allocator_1 : entity work.vc_allocator -- use the less cmplx/performant one
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vc_allocator_1 : entity work.vc_allocator_high_perf -- use the more cmplx/performant one
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generic map (
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port_num => port_num,
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port_exist => port_exist,
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Xis => Xis,
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Yis => Yis,
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Zis => Zis,
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header_incl_in_packet_length => header_incl_in_packet_length,
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rout_algo => rout_algo,
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vc_num_vec => vc_num_vec,
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vc_num_out_vec => vc_num_out_vec)
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port map (
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clk => clk,
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rst => rst,
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header => header,
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enr_vc => vc_transfer_vec_int,
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valid_data_vc_vec => valid_data_vc_vec,
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input_vc_in_use => input_vc_in_use,
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crossbar_ctrl_vec => crossbar_ctrl_vec,
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vc_sel_enc_vec => vc_sel_enc_vec,
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output_vc_in_use => output_vc_in_use);
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switch_allocator_1 : entity work.switch_allocator
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generic map (
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port_num => port_num,
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port_exist => port_exist,
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vc_num_vec => vc_num_vec,
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vc_num_out_vec => vc_num_out_vec,
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vc_depth_array => vc_depth_array,
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vc_depth_out_array => vc_depth_out_array,
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rout_algo => rout_algo)
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port map (
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clk => clk,
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rst => rst,
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input_vc_in_use => input_vc_in_use,
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output_vc_in_use => output_vc_in_use,
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crossbar_ctrl_vec => crossbar_ctrl_vec,
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vc_sel_enc_vec => vc_sel_enc_vec,
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valid_data_vc_vec => valid_data_vc_vec,
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incr_rx_vec => incr_rx_vec,
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crossbar_ctrl => crossbar_ctrl,
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vc_transfer_vec => vc_transfer_vec_int,
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vc_write_tx_vec => vc_write_tx_vec);
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vc_transfer_vec <= vc_transfer_vec_int;
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end architecture structural;
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