142 lines
6 KiB
VHDL
142 lines
6 KiB
VHDL
-------------------------------------------------------------------------------
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-- Title : Router with buffered outputs (pipeline stage)
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-- Project :
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-------------------------------------------------------------------------------
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-- File : router_pl.vhd
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-- Author : Lennart Bamberg <lennart@t440s>
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-- Company :
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-- Created : 2018-11-23
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-- Last update: 2018-11-28
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-- Platform :
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-- Standard : VHDL'93/02
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-------------------------------------------------------------------------------
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-- Description:
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-------------------------------------------------------------------------------
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-- Copyright (c) 2018
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-------------------------------------------------------------------------------
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-- Revisions :
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-- Date Version Author Description
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-- 2018-11-23 1.0 lennart Created
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.NOC_3D_PACKAGE.all;
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entity router_pl is
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generic (
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port_num : integer := 7;
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Xis : natural := 1;
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Yis : natural := 1;
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Zis : natural := 1;
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header_incl_in_packet_length : boolean := true;
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-- integer vector of range "0 to port_num-1"
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port_exist : integer_vec := (0, 1, 2, 3, 4, 5, 6);
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vc_num_vec : integer_vec := (4 ,4 ,4 ,4 ,4 ,4 ,4 );
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vc_num_out_vec : integer_vec := (4 ,4 ,4 ,4 ,4 ,4 ,4 );
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-- integer vector of range "0 to port_num-1, 0 to max_vc_num-1"
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vc_depth_array : vc_prop_int_array := ((4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) );
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vc_depth_out_array : vc_prop_int_array := ((4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) ,(4 ,4 ,4 ,4 ) );
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rout_algo : string := "DXYU"
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);
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port (
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-- Inputs
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clk, rst : in std_logic;
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data_rx : in flit_vector(port_num-1 downto 0);
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vc_write_rx_vec : in std_logic_vector(int_vec_sum(vc_num_vec)-1 downto 0);
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incr_rx_vec : in std_logic_vector(int_vec_sum(vc_num_out_vec)-1 downto 0);
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-- Outputs
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data_tx_pl : out flit_vector(port_num-1 downto 0);
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vc_write_tx_pl_vec : out std_logic_vector(int_vec_sum(vc_num_out_vec)-1 downto 0);
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incr_tx_pl_vec : out std_logic_vector(int_vec_sum(vc_num_vec)-1 downto 0));
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end entity router_pl;
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architecture structural of router_pl is
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signal vc_transfer_vec : std_logic_vector(int_vec_sum(vc_num_vec)-1 downto 0);
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signal valid_data_vc_vec : std_logic_vector(int_vec_sum(vc_num_vec)-1 downto 0);
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signal data_transfer, data_tx : flit_vector(port_num-1 downto 0);
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signal header : header_inf_vector(int_vec_sum(vc_num_vec)-1 downto 0);
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signal crossbar_ctrl : std_logic_vector(port_num*bit_width(port_num-1)-1 downto 0);
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signal vc_write_tx_vec : std_logic_vector(int_vec_sum(vc_num_out_vec)-1 downto 0);
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begin -- architecture structural
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INBUT_BUFFS : for i in 0 to port_num-1 generate
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constant ur_vc : natural := upper_range(vc_num_vec, i);
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constant lr_vc : natural := lower_range(vc_num_vec, i);
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begin
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vc_input_buffer_i : entity work.vc_input_buffer
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generic map (
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vc_num => vc_num_vec(i),
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vc_depth => vc_depth_array(i))
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port map (
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clk => clk,
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rst => rst,
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data_rx => data_rx(i),
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vc_write_rx => vc_write_rx_vec(ur_vc downto lr_vc),
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vc_transfer => vc_transfer_vec(ur_vc downto lr_vc),
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valid_data_vc => valid_data_vc_vec(ur_vc downto lr_vc),
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data_transfer => data_transfer(i),
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header => header(ur_vc downto lr_vc));
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end generate;
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XBAR : entity work.crossbar
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generic map (
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port_num => port_num,
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port_exist => port_exist,
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rout_algo => rout_algo)
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port map (
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crossbar_in => data_transfer,
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crossbar_ctrl => crossbar_ctrl,
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crossbar_out => data_tx);
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OUT_PL_REG : for i in 0 to port_num-1 generate
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constant ur_vc_out : natural := upper_range(vc_num_out_vec, i);
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constant lr_vc_out : natural := lower_range(vc_num_out_vec, i);
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constant ur_vc : natural := upper_range(vc_num_vec, i);
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constant lr_vc : natural := lower_range(vc_num_vec, i);
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begin
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output_register_i : entity work.output_register
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generic map (
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vc_num => vc_num_vec(i),
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vc_num_out => vc_num_out_vec(i))
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port map (
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clk => clk,
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rst => rst,
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data_tx => data_tx(i),
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vc_write_tx => vc_write_tx_vec(ur_vc_out downto lr_vc_out),
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incr_tx => vc_transfer_vec(ur_vc downto lr_vc),
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data_tx_pl => data_tx_pl(i),
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vc_write_tx_pl => vc_write_tx_pl_vec(ur_vc_out downto lr_vc_out),
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incr_tx_pl => incr_tx_pl_vec(ur_vc downto lr_vc));
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end generate;
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CTRL_ARB : entity work.arbiter
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generic map (
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port_num => port_num,
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port_exist => port_exist,
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Xis => Xis,
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Yis => Yis,
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Zis => Zis,
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header_incl_in_packet_length => header_incl_in_packet_length,
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rout_algo => rout_algo,
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vc_num_vec => vc_num_vec,
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vc_num_out_vec => vc_num_out_vec,
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vc_depth_array => vc_depth_array,
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vc_depth_out_array => vc_depth_out_array)
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port map (
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clk => clk,
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rst => rst,
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header => header,
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valid_data_vc_vec => valid_data_vc_vec,
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incr_rx_vec => incr_rx_vec,
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crossbar_ctrl => crossbar_ctrl,
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vc_transfer_vec => vc_transfer_vec,
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vc_write_tx_vec => vc_write_tx_vec);
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end architecture structural;
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