61 lines
2.4 KiB
VHDL
61 lines
2.4 KiB
VHDL
-------------------------------------------------------------------------------
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-- Title : Mux-based crossbar (full connectivity)
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-- Project : Modular, heterogenous 3D NoC
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-------------------------------------------------------------------------------
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-- File : crossbar_full.vhd
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-- Author : Lennart Bamberg <bamberg@office.item.uni-bremen.de>
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-- Company :
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-- Created : 2018-10-24
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-- Last update: 2018-11-28
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-- Platform :
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-- Standard : VHDL'93/02
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-------------------------------------------------------------------------------
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-- Description: Crossbar to connect the inputs to the outputs with the help of
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-- multiplexers (U-turns are avoided).
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-------------------------------------------------------------------------------
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-- Copyright (c) 2018
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-------------------------------------------------------------------------------
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-- Revisions :
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-- Date Version Author Description
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-- 2018-10-24 1.0 bamberg Created
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use IEEE.math_real.all;
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use ieee.numeric_std.all;
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use work.NOC_3D_PACKAGE.all;
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entity crossbar_full is
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generic(port_num : positive := 7);
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port (crossbar_in : in flit_vector(port_num-1 downto 0);
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crossbar_ctrl : in std_logic_vector(
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port_num*bit_width(port_num-1)-1 downto 0);
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crossbar_out : out flit_vector(port_num-1 downto 0));
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end entity crossbar_full;
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architecture rtl of crossbar_full is
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constant port_sel_width : positive := bit_width(port_num-1); -- bits for the
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-- crossbar_ctrl signal of
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-- one output port
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type multiplexer_input_type is array (port_num-1 downto 0)
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of flit_vector(port_num-2 downto 0);
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signal multiplexer_input : multiplexer_input_type;
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begin
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multiplexer_input(0) <= crossbar_in(port_num-1 downto 1);
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INPUT_GEN : for i in 1 to port_num-1 generate
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begin
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multiplexer_input(i) <= crossbar_in(i-1 downto 0)
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& crossbar_in(port_num-1 downto i+1);
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end generate;
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MULT_GEN : for i in 0 to port_num-1 generate
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begin
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crossbar_out(i) <= multiplexer_input(i)(to_integer(
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unsigned(crossbar_ctrl((i+1)*port_sel_width-1 downto i*port_sel_width)))
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);
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end generate;
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end architecture rtl;
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