73 lines
2.1 KiB
VHDL
73 lines
2.1 KiB
VHDL
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-- hu_ctr
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-- Control path for Update H using stream of weights
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use work.pkg_sbs.all;
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entity hu_ctr is
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port (
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clk, rstn : in bit;
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cfg_hu : in bit_vector(BW_HU_CFG -1 downto 0); -- Config
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ena_w : in bit; -- New weight
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is_ini : in bit; -- First vector (get w and h when ena)
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is_fst : in bit; -- Fist component in vector
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loc_h : in bit_vector(ADDR_H_MAX-1 downto 0); -- Current location in H
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ena_ho : out bit; -- Signal a valid ho value
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eps : out real;
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ctr_hu : out bit_vector(BW_HU_CTR-1 downto 0)); -- Control for data path
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end entity hu_ctr;
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library ieee;
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use ieee.numeric_bit.all;
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architecture beh of hu_ctr is
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signal ctr_sel_ini, ctr_sum_ini, ctr_update_sum, ctr_update_sum2 : bit;
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signal ctr_addr_rst, ctr_addr_inc, ctr_write_hw : bit;
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signal ctr_wr_hw, ctr_wr_hp : bit;
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-- Number of elements in H (currently fixed)
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constant MAX_LOC_H : bit_vector(ADDR_H_MAX-1 downto 0) := bit_vector(to_unsigned(8, ADDR_H_MAX));
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--constant T : time := 10 ns;
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begin -- architecture beh
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eps <= 0.2;
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ctr_hu(0) <= ctr_sel_ini ;
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ctr_hu(1) <= ctr_sum_ini ;
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ctr_hu(2) <= ctr_update_sum ;
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ctr_hu(3) <= ctr_addr_rst ;
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ctr_hu(4) <= ctr_addr_inc ;
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ctr_hu(5) <= ctr_write_hw ;
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ctr_hu(6) <= ctr_wr_hw ;
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--ctr_hu(7) <= ctr_wr_hp ; -- ctr_wr_hp and ctr_wr_hw are the same
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ctr_hu(7) <= ctr_update_sum2 ;
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-- Code in first approximation
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ctr_sel_ini <= is_ini;
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ctr_wr_hp <= ena_w; --is_ini;
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ctr_wr_hw <= ena_w;
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ctr_sum_ini <= is_fst;
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ctr_update_sum <= transport is_fst after 7*T ;
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--ctr_update_sum2 <= transport ctr_update_sum after T;
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--ctr_update_sum <= '1' when (loc_h = MAX_LOC_H) else '0';
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ctr_addr_rst <= ctr_update_sum;
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ctr_addr_inc <= ena_w and not ctr_addr_rst;
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ena_ho <= ena_w and not is_ini;
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rg: process (clk, rstn) is
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begin
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if rstn = '0' then -- asynchronous reset (active low)
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ctr_update_sum2 <= '0';
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elsif clk'event and clk = '1' then -- rising clock edge
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ctr_update_sum2 <= ctr_update_sum;
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end if;
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end process rg;
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end architecture beh;
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