wk_sbs_hdl/hw/beh/tst_pkg_ufp.vhd

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VHDL
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use work.pkg_ufp.all;
entity tst_pkg_ufp is
end entity tst_pkg_ufp;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture tst of tst_pkg_ufp is
begin -- architecture tst
process
-- Define params of ufp
constant BW : natural := 10;
constant BE : natural := 3;
constant EO : natural := 1;
constant BO : natural := BW - BE -EO;
variable r, r2 : real;
variable ee_mm : std_logic_vector(BW-1 downto 0);
variable mm : std_logic_vector(BW-1-BE downto 0);
variable ee : std_logic_vector(BE-1 downto 0);
constant r_ini : real := 0.0125;
constant r_inc : real := 0.0125/4.0;
constant N : natural := 10;
procedure print (
ar : in real;
aee : in std_logic_vector(BE-1 downto 0);
amm : in std_logic_vector(BW-1-BE downto 0)) is
begin
report LF & "[TST] " &
"r=" & real'image(ar) & HT & HT &
"ufp= " & integer'image(to_integer(unsigned(amm))) &
" *2**(-" & integer'image(BO) & "- " & integer'image(to_integer(unsigned(aee))) & " )"
severity note;
end procedure;
procedure tst_conv_r (
aee : in std_logic_vector(BE-1 downto 0);
amm : in std_logic_vector(BW-1-BE downto 0)) is
variable ar : real;
variable aee_mm : std_logic_vector(BW-1 downto 0);
begin -- procedure tst_conv_r
aee_mm := aee & amm;
ar := ufp_to_real(aee_mm, BW, BE, EO);
print(ar, aee, amm);
aee_mm := real_to_ufp(ar, BW, BE, EO);
print(ar, aee, amm);
report LF & "[TST] ----------------------------------" severity note;
end procedure tst_conv_r;
constant ee_0min : std_logic_vector(BE-1 downto 0) := (others => '0');
constant ee_1min : std_logic_vector(BE-1 downto 0) := (0 => '1', others => '0');
constant ee_2min : std_logic_vector(BE-1 downto 0) := (1 => '1', others => '0');
constant ee_0max : std_logic_vector(BE-1 downto 0) := (others => '1');
constant ee_1max : std_logic_vector(BE-1 downto 0) := (0 => '0', others => '1');
constant ee_2max : std_logic_vector(BE-1 downto 0) := (1 => '0', others => '1');
constant mm_0min : std_logic_vector(BW-1-BE downto 0) := (others => '0');
constant mm_1min : std_logic_vector(BW-1-BE downto 0) := (0 => '1', others => '0');
constant mm_2min : std_logic_vector(BW-1-BE downto 0) := (1 => '1', others => '0');
constant mm_0max : std_logic_vector(BW-1-BE downto 0) := (others => '1');
constant mm_1max : std_logic_vector(BW-1-BE downto 0) := (0 => '0', others => '1');
constant mm_2max : std_logic_vector(BW-1-BE downto 0) := (1 => '0', others => '1');
begin
if true then
report LF & "[TST] Test corner examples =============================" severity note;
-- Conversion from ee_mm to real
tst_conv_r(ee_0max, mm_0min);
tst_conv_r(ee_0max, mm_1min);
tst_conv_r(ee_0max, mm_2min);
tst_conv_r(ee_0max, mm_2max);
tst_conv_r(ee_0max, mm_1max);
tst_conv_r(ee_0max, mm_0max);
tst_conv_r(ee_1max, mm_0min);
tst_conv_r(ee_1max, mm_1min);
tst_conv_r(ee_1max, mm_2min);
tst_conv_r(ee_1max, mm_2max);
tst_conv_r(ee_1max, mm_1max);
tst_conv_r(ee_1max, mm_0max);
tst_conv_r(ee_1min, mm_0min);
tst_conv_r(ee_1min, mm_1min);
tst_conv_r(ee_1min, mm_2min);
tst_conv_r(ee_1min, mm_2max);
tst_conv_r(ee_1min, mm_1max);
tst_conv_r(ee_1min, mm_0max);
tst_conv_r(ee_0min, mm_0min);
tst_conv_r(ee_0min, mm_1min);
tst_conv_r(ee_0min, mm_2min);
tst_conv_r(ee_0min, mm_2max);
tst_conv_r(ee_0min, mm_1max);
tst_conv_r(ee_0min, mm_0max);
end if;
if true then
report LF & "[TST] Test ramp =============================" severity note;
-- Conersion from real to ee_mm
r:= r_ini;
for ki in 0 to N-1 loop
ee_mm := real_to_ufp(r, BW, BE, EO);
ee := ee_mm(BW-1 downto BW-BE);
mm := ee_mm(BW-BE-1 downto 0);
print(r, ee, mm);
r2 := ufp_to_real(ee_mm, BW, BE, EO);
print(r2, ee, mm);
report LF & "[TST] ----------------------------------" severity note;
r := r + r_inc;
end loop; -- ki
end if;
`
wait;
end process;
end architecture tst;