53 lines
1.4 KiB
VHDL
53 lines
1.4 KiB
VHDL
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-- Simple multiply with adder to check speed
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity mua is
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generic (
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B : natural := 10); -- bitwidth
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port (
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clk, arstn : in std_logic;
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dt_mv, dt_mc : in std_logic_vector(B-1 downto 0); -- input for multiplicatin
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dt_add : in std_logic_vector(2*B-1 downto 0); -- constant to add
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dt_mua : out std_logic_vector(2*B-1 downto 0)); -- output
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end entity mua;
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library ieee;
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use ieee.numeric_std.all;
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architecture rtl of mua is
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signal dt_mv_rg, dt_mc_rg : unsigned(B-1 downto 0);
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signal dt_add_rg : unsigned(2*B-1 downto 0);
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signal dt_mua_rg, dt_mua_nxt : unsigned(2*B-1 downto 0);
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begin -- architecture rtl
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dt_mua_nxt <= dt_mv_rg * dt_mc_rg + dt_add_rg;
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dt_mua <= std_logic_vector(dt_mua_rg);
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reg: process (clk, arstn) is
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begin -- process reg
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if arstn = '0' then -- asynchronous reset (active low)
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dt_mv_rg <= (others=>'0');
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dt_mc_rg <= (others=>'0');
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dt_add_rg <= (others=>'0');
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dt_mua_rg <= (others=>'0');
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elsif clk'event and clk = '1' then -- rising clock edge
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dt_mv_rg <= unsigned(dt_mv);
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dt_mc_rg <= unsigned(dt_mc);
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dt_add_rg <= unsigned(dt_add);
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dt_mua_rg <= dt_mua_nxt;
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end if;
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end process reg;
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end architecture rtl;
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