127 lines
3.4 KiB
VHDL
127 lines
3.4 KiB
VHDL
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-- tst_hu
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-- Testbench for Update H using stream of weights
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use work.pkg_sbs.all;
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entity tst_hu is
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end entity tst_hu;
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architecture tst of tst_hu is
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constant T : time := 10 ns; -- Period
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signal clk, rstn : bit := '0';
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signal cfg_hu : bit_vector(BW_HU_CFG -1 downto 0);
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signal ena_w : bit;
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signal is_ini : bit;
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signal is_fst : bit;
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signal ena_ho : bit;
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signal wi : real := 0.0;
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signal hi : real := 0.0;
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signal ho : real;
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begin -- architecture tst
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clk <= not clk after T/2;
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rstn <= '0', '1' after T/2+T/4;
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i_hu: entity work.hu
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port map (
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clk => clk,
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rstn => rstn,
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cfg_hu => cfg_hu,
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ena_w => ena_w,
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is_ini => is_ini,
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is_fst => is_fst,
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ena_ho => ena_ho,
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wi => wi,
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hi => hi,
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ho => ho);
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process (clk) is
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type array_sol is array (natural range <>) of real;
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-- Example of solution from python
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constant h_sol : array_sol := (
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--0.1 , 0.2 , 0.3 , 0.0 , 0.01, 0.01, 0.1 , 0.28,
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0.01628 , 0.02056 , 0.03144 , 0.0 , 0.001228, 0.001588, 0.01228 , 0.039984,
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1.28343706e-04, 1.62085171e-04, 3.17669760e-04, 0.00000000e+00, 1.24077120e-05, 1.99630656e-05, 1.84671552e-04, 3.05349811e-04,
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2.17637063e-08, 2.74853687e-08, 5.38684101e-08, 0.00000000e+00, 2.10402060e-09, 3.38520923e-09, 3.13154230e-08, 5.17792718e-08
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);
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variable idx : natural;
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begin -- process
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if clk'event and clk = '1' then -- rising clock edge
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if ena_ho='1' then
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if idx<h_sol'length-1 then
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if abs(ho-h_sol(idx)) > 1.0e-09 then
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report LF & ESC & "[31;1m [ERROR] h_sol= " & real'image(h_sol(idx)) & ESC & "[0m" & LF severity error;
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end if;
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idx := idx+1;
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end if;
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report LF & "[INFO] h_exp= " & real'image(ho) & LF severity note;
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end if;
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end if;
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end process;
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process is
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constant h : array_as_h := (0.1, 0.2, 0.3, 0.0, 0.01, 0.01, 0.1, 0.28);
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begin -- process
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hi <= 0.0;
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is_ini <= '0';
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wait for T/4 + T/2 + T;
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for n in 0 to 1 loop
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for ki in h'range loop
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hi <= h(ki);
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is_ini <= '1';
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wait for T;
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end loop; -- ki
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is_ini <= '0';
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hi <= 0.0;
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--wait for T*(h'length+1)*3; -- note +1 for void cycle
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wait for T*(2+(h'length+2)*3); -- note +2 for void cycle
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end loop; -- n
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wait;
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end process;
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process is
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constant w0 : array_as_h := (0.3, 0.0, 0.01, 0.01, 0.1, 0.28, 0.1, 0.2);
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constant w1 : array_as_h := (0.01, 0.01, 0.1, 0.28, 0.1, 0.2, 0.3, 0.0);
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constant w2 : array_as_h := (0.125, 0.125, 0.125, 0.125, 0.125, 0.125, 0.125, 0.125);
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type array_w is array (0 to 2) of array_as_h;
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constant w : array_w := (w0, w1, w2);
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begin -- process
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ena_w <= '0';
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wi <= 0.0;
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wait for T/4 + T/2 + T;
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for n in 0 to 1 loop
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for kj in w'range loop
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is_fst <= '1', '0' after T;
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for ki in w0'range loop
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ena_w <= '1';
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wi <= w(kj)(ki);
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wait for T;
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end loop; -- ki
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ena_w <= '0'; -- void cycle
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wait for 2*T; --
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end loop; -- kj
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end loop; -- n
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ena_w <= '0';
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wait for 4*T;
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report LF & LF & ESC & "[35;1m [TST] End simulation" & ESC & "[0m" & LF severity failure;
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end process;
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end architecture tst;
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