66 lines
2.1 KiB
VHDL
66 lines
2.1 KiB
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity mult_unsgn_pp_trunc is
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generic (
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BWa : natural := 16; -- Bit width of Multiplier
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BWb : natural := 16;
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K : natural := 15); -- Vertical truncation
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port (
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da : in std_logic_vector(BWa-1 downto 0);
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db : in std_logic_vector(BWb-1 downto 0);
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dout : out std_logic_vector(BWa+BWb-1 downto 0));
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end mult_unsgn_pp_trunc;
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architecture str of mult_unsgn_pp_trunc is
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type stlv_array is array (0 to BWa-1) of std_logic_vector(BWa+BWb-2 downto 0);
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signal pp : stlv_array;
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--signal pp_res : std_logic_vector(BWa+BWb-1 downto 0);
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begin -- str
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ppGen : process (da, db)
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variable ppt : stlv_array;
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begin
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ppt := (others => (others => '0'));
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-- partial products da(i)db(j) EX:
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-- da(0)db(3) da(0)db(2) da(0)db(1) da(0)db(0)
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-- da(1)db(3) da(1)db(2) da(1)db(1) da(1)db(0)
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-- da(2)db(3) da(2)db(2) da(2)db(1) da(2)db(0)
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-- da(3)db(3) da(3)db(2) da(3)db(1) da(3)db(0)
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for i in 0 to BWa-1 loop
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for j in 0 to BWb-1 loop
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if (i+j > K-1) then
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ppt(i)(i+j) := da(i) and db(j);
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end if;
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end loop;
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end loop;
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PP <= ppt;
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end process ppGen;
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CSA_tree : process (pp)
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variable pp_add : std_logic_vector(BWa+BWb-1 downto 0);
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begin -- process CSA_tree
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for i in 0 to BWa-1 loop
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if i = 0 then
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pp_add := '0' & pp(0)(BWa+BWb-2 downto 0);
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else
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pp_add := std_logic_vector(unsigned('0'&pp(i)(BWa+BWb-2 downto 0)) + unsigned(pp_add));
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end if;
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end loop; -- i
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--pp_res <= pp_add;
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dout <= pp_add;
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end process CSA_tree;
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-- dout <= pp_res;
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--dout(BWa+BWb-1 downto 16) <= pp_res(BWa+BWb-1 downto 16);
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--dout(15 downto 0) <= (others => '0');
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end str;
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