149 lines
4.5 KiB
VHDL
149 lines
4.5 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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use work.real_vector_pkg.all; -- Import the real_vector and real_matrix definitions
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entity tb_dptc_basic is
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end entity;
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architecture Behavioral_basic of tb_dptc_basic is
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-- Constants
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constant Nv : integer := 2; -- Rows
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constant Nh : integer := 2; -- Columns
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constant N : integer := 4; -- Vector size inside each DDot
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-- DUT Signals
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signal clk : std_logic := '0';
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signal reset_n : std_logic := '0';
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signal enable : std_logic := '0';
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signal out_valid : std_logic;
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signal x_matrix : my_real_matrix(0 to Nv-1, 0 to N-1);
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signal y_matrix : my_real_matrix(0 to Nh-1, 0 to N-1);
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signal result_matrix : real_matrix(0 to Nv-1, 0 to Nh-1);
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-- Clock period
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constant clk_period : time := 10 ns;
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begin
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-- Instantiate DUT
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uut: entity work.dptc
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generic map (
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Nv => Nv,
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Nh => Nh,
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N => N
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)
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port map (
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clk => clk,
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reset_n => reset_n,
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enable => enable,
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x_matrix => x_matrix,
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y_matrix => y_matrix,
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out_valid => out_valid,
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result_matrix => result_matrix
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);
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-- Clock generation
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clk_process : process
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begin
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clk <= '0';
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wait for clk_period/2;
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clk <= '1';
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wait for clk_period/2;
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end process;
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-- Stimulus process
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stim_proc: process
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begin
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-- Reset the system
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reset_n <= '0';
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enable <= '0';
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wait for 20 ns;
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reset_n <= '1';
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wait for clk_period;
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-- Apply test inputs
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-- X Matrix (2x4)
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x_matrix(0,0) <= 1.0; x_matrix(0,1) <= 2.0; x_matrix(0,2) <= 3.0; x_matrix(0,3) <= 4.0;
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x_matrix(1,0) <= 5.0; x_matrix(1,1) <= 6.0; x_matrix(1,2) <= 7.0; x_matrix(1,3) <= 8.0;
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-- Y Matrix (2x4)
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y_matrix(0,0) <= 1.0; y_matrix(0,1) <= 0.0; y_matrix(0,2) <= 1.0; y_matrix(0,3) <= 0.0;
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y_matrix(1,0) <= 0.0; y_matrix(1,1) <= 1.0; y_matrix(1,2) <= 0.0; y_matrix(1,3) <= 1.0;
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-- Enable operation
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wait for clk_period;
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enable <= '1';
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wait until rising_edge(clk) and out_valid = '1'; -- Wait for computation to complete
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enable <= '0';
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-- Wait to observe outputs
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wait for 50 ns;
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-- Report the result
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report "Result Matrix (After Multiplication): ";
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report "Row 0, Col 0: " & real'image(result_matrix(0,0));
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report "Row 0, Col 1: " & real'image(result_matrix(0,1));
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report "Row 1, Col 0: " & real'image(result_matrix(1,0));
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report "Row 1, Col 1: " & real'image(result_matrix(1,1));
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--new input
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wait for 50 ns;
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-- Apply test inputs
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-- X Matrix (2x4)
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x_matrix(0,0) <= 2.0; x_matrix(0,1) <= 4.0; x_matrix(0,2) <= 1.0; x_matrix(0,3) <= 1.0;
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x_matrix(1,0) <= 4.0; x_matrix(1,1) <= 3.0; x_matrix(1,2) <= 4.0; x_matrix(1,3) <= 3.0;
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-- Y Matrix (2x4)
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y_matrix(0,0) <= 0.0; y_matrix(0,1) <= 1.0; y_matrix(0,2) <= 2.0; y_matrix(0,3) <= 3.0;
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y_matrix(1,0) <= 1.0; y_matrix(1,1) <= 1.0; y_matrix(1,2) <= 1.0; y_matrix(1,3) <= 0.0;
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-- Enable operation
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wait for clk_period;
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enable <= '1';
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wait until rising_edge(clk) and out_valid = '1'; -- Wait for computation to complete
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enable <= '0';
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-- Wait to observe outputs
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wait for 50 ns;
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-- Report the result
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report "Result Matrix (After Multiplication): ";
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report "Row 0, Col 0: " & real'image(result_matrix(0,0));
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report "Row 0, Col 1: " & real'image(result_matrix(0,1));
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report "Row 1, Col 0: " & real'image(result_matrix(1,0));
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report "Row 1, Col 1: " & real'image(result_matrix(1,1));
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-- 3rd input
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wait for 50 ns;
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x_matrix(0,0) <= 1.0; x_matrix(0,1) <= 2.0; x_matrix(0,2) <= 5.0; x_matrix(0,3) <= 6.0;
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x_matrix(1,0) <= 3.0; x_matrix(1,1) <= 3.0; x_matrix(1,2) <= 7.0; x_matrix(1,3) <= 2.0;
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-- Y Matrix (2x4)
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y_matrix(0,0) <= 1.0; y_matrix(0,1) <= 4.0; y_matrix(0,2) <= 1.0; y_matrix(0,3) <= 0.0;
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y_matrix(1,0) <= 2.0; y_matrix(1,1) <= 3.0; y_matrix(1,2) <= 1.0; y_matrix(1,3) <= 1.0;
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-- Enable operation
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wait for clk_period;
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enable <= '1';
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wait until rising_edge(clk) and out_valid = '1'; -- Wait for computation to complete
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enable <= '0';
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-- Wait to observe outputs
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wait for 50 ns;
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-- Report the result
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report "Result Matrix (After Multiplication): ";
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report "Row 0, Col 0: " & real'image(result_matrix(0,0));
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report "Row 0, Col 1: " & real'image(result_matrix(0,1));
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report "Row 1, Col 0: " & real'image(result_matrix(1,0));
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report "Row 1, Col 1: " & real'image(result_matrix(1,1));
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wait; -- End of simulation
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end process;
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end architecture;
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