96 lines
2 KiB
VHDL
96 lines
2 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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use work.real_vector_pkg.all;
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entity tb_ddot_unit is
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end tb_ddot_unit;
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architecture Behavioral of tb_ddot_unit is
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-- Parameters
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constant N : integer := 4; -- must match DDOT generic
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-- DUT signals
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signal clk : std_logic := '0';
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signal reset_n : std_logic := '0';
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signal enable : std_logic := '0';
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signal out_valid : std_logic;
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signal x_vec : my_real_vector(0 to N-1);
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signal y_vec : my_real_vector(0 to N-1);
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signal dot_out : real;
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-- Clock period
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constant clk_period : time := 10 ns;
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begin
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-- Instantiate the DUT
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uut: entity work.ddot_unit
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generic map (
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N => N
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)
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port map (
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clk => clk,
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reset_n => reset_n,
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enable => enable,
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x_vec => x_vec,
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y_vec => y_vec,
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out_valid => out_valid,
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dot_out => dot_out
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);
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-- Clock generation
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clk_process : process
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begin
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clk <= '0';
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wait for clk_period/2;
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clk <= '1';
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wait for clk_period/2;
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end process;
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-- Stimulus process
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stim_proc: process
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begin
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-- Reset
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reset_n <= '0';
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enable <= '0';
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wait for 20 ns;
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reset_n <= '1';
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wait for 10 ns;--
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-- Apply first test vector
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x_vec(0) <= 1.0; y_vec(0) <= 2.0;
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x_vec(1) <= 3.0; y_vec(1) <= 4.0;
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x_vec(2) <= 5.0; y_vec(2) <= 6.0;
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x_vec(3) <= 7.0; y_vec(3) <= 8.0;
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wait for clk_period;--
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enable <= '1';
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wait until rising_edge(clk) and out_valid = '1';
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--wait for 10 ns;
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enable <= '0';
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-- Wait and observe output
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wait for 50 ns;
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-- Apply second test vector
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x_vec(0) <= 2.0; y_vec(0) <= 3.0;
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x_vec(1) <= 4.0; y_vec(1) <= 5.0;
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x_vec(2) <= 6.0; y_vec(2) <= 7.0;
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x_vec(3) <= 8.0; y_vec(3) <= 9.0;
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wait for clk_period;
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enable <= '1';
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wait until rising_edge(clk) and out_valid = '1';
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--wait for 10 ns;
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enable <= '0';
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-- Wait and observe output
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wait for 50 ns;
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-- Finish simulation
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wait;
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end process;
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end architecture;
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