jneyra/paicore_behavioral
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base: jneyra:8b3a01c19a1ed508ea40a34d50d25c8ef60431e6
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compare: jneyra:f3cbca90d10c33c2163c8bbd6ba8a148d65bf60d
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2 commits
8b3a01c19a ... f3cbca90d1

Author SHA1 Message Date
Retrocamara42
f3cbca90d1 fix: core_pos size corrected 2025-07-03 08:47:38 -05:00
Retrocamara42
977951d080 fix: core_pos size corrected 2025-07-03 08:47:28 -05:00
3 changed files with 8 additions and 7 deletions
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10
router/router.vhdl
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@ -13,8 +13,8 @@ generic (
buffer_width : integer := 64;
buffer_depth : integer := 4;
fifo_ptr_size : integer := 3;
chip_x : std_logic_vector(4 downto 0) := "00000";
chip_y : std_logic_vector(4 downto 0) := "00000"
chip_x : std_logic_vector(DEST_ADDR_SIZE-1 downto 0) := "00000";
chip_y : std_logic_vector(DEST_ADDR_SIZE-1 downto 0) := "00000"
);
port (
clk : in std_logic;
@ -34,7 +34,7 @@ architecture impl of router is
constant TOT_NUM_PATHS : integer := num_paths_up + num_paths_down*4;
constant chip_pos : t_chip_addr := (x => chip_x, y=> chip_y);
signal core_pos : t_addr;
signal core_pos : t_core_addr;
signal rcv_buff_out : t_FIFO_OUTS(TOT_NUM_PATHS-1 downto 0);
signal snd_buff_wr_in : t_FIFO_WR_INS(TOT_NUM_PATHS-1 downto 0);
signal snd_buff_out : t_FIFO_OUTS(num_paths_up+num_paths_down*4-1 downto 0);
@ -241,6 +241,6 @@ begin
end if;
end process;
core_pos.x <= core_x;
core_pos.y <= core_y;
core_pos.x <= core_x(DEST_ADDR_SIZE-1 downto 1);
core_pos.y <= core_y(DEST_ADDR_SIZE-1 downto 1);
end impl;

4
router/router_components.vhdl
View file

@ -44,7 +44,7 @@ package router_components is
);
port (
chip_pos : in t_chip_addr;
core_pos : in t_addr;
core_pos : in t_core_addr;
packets : in t_DATA(num_paths_up+num_paths_down*4-1 downto 0);
valid_data : in std_logic_vector(
num_paths_up+num_paths_down*4-1 downto 0);
@ -65,7 +65,7 @@ package router_components is
);
port (
chip_pos : in t_chip_addr;
core_pos : in t_addr;
core_pos : in t_core_addr;
packets : in t_DATA(num_paths_up*4+num_paths_down*4-1 downto 0);
valid_data : in std_logic_vector(num_paths_up*4+num_paths_down*4-1 downto 0);
avai_paths : in std_logic_vector(num_paths_up*4+num_paths_down*4-1 downto 0);

1
synthesis/cmd/do_synth_router.tcl
View file

@ -11,6 +11,7 @@ analyze -library WORK -format vhdl {../router/receiver.vhdl}
analyze -library WORK -format vhdl {../router/sender.vhdl}
analyze -library WORK -format vhdl {../router/arbiter.vhdl}
link
analyze -library WORK -format vhdl {../router/router_components.vhdl}
analyze -library WORK -format vhdl {../router/router.vhdl}
elaborate router -library WORK -parameters
"level = $level, num_paths_up = $npu, num_paths_down = $npd,