fix: no clk in arbiter

router/router_types.vhdl

@@ -47,8 +47,8 @@ package router_types is
     end record;
 
     type t_addr is record
-        x :   std_logic_vector(DEST_ADDR_SIZE-1 downto 0);
-        y :   std_logic_vector(DEST_ADDR_SIZE-1 downto 0);
+        x :   std_logic_vector(DEST_ADDR_SIZE-1 downto 1); -- last bit is always '-' for all routers
+        y :   std_logic_vector(DEST_ADDR_SIZE-1 downto 1);
     end record;
 
     type t_pos_addr is record

synthesis/cmd/do_synth_arbiter.tcl

@@ -7,19 +7,6 @@ analyze -library WORK -format vhdl {../router/routing_functions.vhdl}
 analyze -library WORK -format vhdl {../router/arbiter.vhdl}
 elaborate arbiter -library WORK -parameters "level = $level, num_paths_up = $npu, num_paths_down = $npd"
 check_design
-
-create_clock [get_ports clk]  -period 8.0  -waveform {0 4} -name clk
-
-set_clock_uncertainty 0.025  -setup [get_clocks clk]
-set_clock_uncertainty 0.025  -hold [get_clocks clk]
-set_clock_transition -fall 0.04 [get_clocks clk]
-set_clock_transition -rise 0.04 [get_clocks clk]
-
-set_clock_latency -max -source 0.1 [get_clocks clk] 
-
-set_input_delay -max -clock clk  0.05 [get_ports {rout_pos packets valid_data avai_paths}]
-set_output_delay -max -clock clk  0.05 [all_outputs]
-
 check_timing
 compile
 report_area > reports/arbiter-$level-spl_synth.area

synthesis/cmd/do_synth_router_lvl1.sh

@@ -1 +1 @@
-LEVEL=1 NPU=2 NPD=1 CHIP_X=00001 CHIP_Y=00001 dc_shell -x "source cmd/do_synth_arbiter.tcl; quit" | tee -a log/synthesis.log
+LEVEL=1 NPU=2 NPD=1 CHIP_X=00001 CHIP_Y=00001 dc_shell -x "source cmd/do_synth_router.tcl; quit" | tee -a log/synthesis.log