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31568263f8
| Author | SHA1 | Date | |
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31568263f8 | ||
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b1431ca815 | ||
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6ce2b810ea | ||
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cfb4469d58 |
23 changed files with 530 additions and 85 deletions
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@ -38,4 +38,5 @@ FIFO5 -> U -> Upstream
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### Router
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-- TODO: Testing Multicast X, Unicast other routers, Broadcast
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-- TODO: Sender and receiver
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-- TODO: interchip communication
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@ -16,7 +16,7 @@ port (
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packets : in t_DATA(num_paths_up+num_paths_down*4-1 downto 0);
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avai_paths : in std_logic_vector(num_paths_up+num_paths_down*4-1 downto 0);
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arb_complete : out std_logic_vector(num_paths_up+num_paths_down*4-1 downto 0);
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buff_wr_in : out t_PORT_WR_IN(num_paths_up+num_paths_down*4-1 downto 0)
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buff_wr_in : out t_FIFO_WR_INS(num_paths_up+num_paths_down*4-1 downto 0)
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--data_out : out t_DATA(num_paths_up+num_paths_down*4-1 downto 0);
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--wr_req : out std_logic_vector(num_paths_up+num_paths_down*4-1 downto 0)
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);
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@ -188,7 +188,7 @@ begin
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end loop;
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end process;
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update_signals: process(clk, arstN)
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update_regs: process(clk, arstN)
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begin
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if arstN = '0' then
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avai_pos <= (others => 0);
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42
receiver.vhdl
Normal file
42
receiver.vhdl
Normal file
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@ -0,0 +1,42 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity Receiver is
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port (
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clk, req, accept_ack : in std_logic;
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data : in std_logic_vector(63 downto 0);
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req_flag, ack : out std_logic;
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data_out : out std_logic_vector(63 downto 0)
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);
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end Receiver;
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architecture impl of Receiver is
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signal req1, req2, req3, req_nxt : std_logic;
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signal req_mux, upd_req, upd_req_nxt : std_logic;
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signal req_edge, ack_nxt, upd_ack : std_logic;
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signal req_flag1, req_flag2, req_flag3 : std_logic;
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signal data_nxt : std_logic_vector(63 downto 0);
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begin
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req_edge <= req2 xor req3;
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upd_ack <= accept_ack and req_flag2;
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req_flag1 <= '1' when req_edge = '1' else '0'
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when upd_ack = '1' else req_flag2;
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ack_nxt <= not ack when (upd_ack) = '1' else ack;
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req_flag <= req_flag3 and (not req_flag2);
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data_nxt <= data when req_edge = '1' else data_out;
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update_regs: process(clk)
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begin
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if rising_edge(clk) then
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req1 <= req;
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req2 <= req1;
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req3 <= req2;
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req_flag2 <= req_flag1;
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req_flag3 <= req_flag2;
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ack <= ack_nxt;
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data_out <= data_nxt;
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end if;
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end process;
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end impl;
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56
router.vhdl
56
router.vhdl
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@ -3,7 +3,6 @@ use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.router_types.all;
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use work.routing_functions.all;
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use work.router_components.all;
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entity router is
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@ -22,21 +21,28 @@ generic (
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port (
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clk : in std_logic;
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arstN : in std_logic;
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rcv_buff_wr_in : in t_PORT_WR_IN(num_paths_up+num_paths_down*4-1 downto 0);
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snd_buff_rd_in : in std_logic_vector(num_paths_up+num_paths_down*4-1 downto 0);
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snd_buff_out : out t_PORT_OUT(num_paths_up+num_paths_down*4-1 downto 0)
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data_in : in t_DATA(num_paths_up+num_paths_down*4-1 downto 0);
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rcv_reqs : in std_logic_vector(num_paths_up+num_paths_down*4-1 downto 0);
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send_ack : in std_logic_vector(num_paths_up+num_paths_down*4-1 downto 0);
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rcv_acks : out std_logic_vector(num_paths_up+num_paths_down*4-1 downto 0);
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send_reqs : out std_logic_vector(num_paths_up+num_paths_down*4-1 downto 0);
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data_out : out t_DATA(num_paths_up+num_paths_down*4-1 downto 0)
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);
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end router;
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architecture impl of router is
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constant TOT_NUM_PATHS : positive := num_paths_up + num_paths_down*4;
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constant TOT_NUM_PATHS : positive := num_paths_up + num_paths_down*4;
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signal rout_pos : t_pos_addr;
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signal rcv_buff_out : t_PORT_OUT(TOT_NUM_PATHS-1 downto 0);
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signal snd_buff_wr_in : t_PORT_WR_IN(TOT_NUM_PATHS-1 downto 0);
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signal snd_buff_out_nxt : t_PORT_OUT(TOT_NUM_PATHS-1 downto 0);
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signal rcv_buff_wr_in : t_FIFO_WR_INS(num_paths_up+num_paths_down*4-1 downto 0);
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signal rcv_buff_out : t_FIFO_OUTS(TOT_NUM_PATHS-1 downto 0);
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signal snd_buff_wr_in : t_FIFO_WR_INS(TOT_NUM_PATHS-1 downto 0);
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signal snd_buff_out : t_FIFO_OUTS(num_paths_up+num_paths_down*4-1 downto 0);
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signal snd_buff_rd_in : std_logic_vector(num_paths_up+num_paths_down*4-1 downto 0);
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signal rcv_accept_ack : std_logic_vector(num_paths_up+num_paths_down*4-1 downto 0);
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signal rd_data, rd_data_nxt : t_DATA(TOT_NUM_PATHS-1 downto 0);
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signal rd_reqs : std_logic_vector(TOT_NUM_PATHS-1 downto 0);
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signal snd_data_rd_reqs : std_logic_vector(TOT_NUM_PATHS-1 downto 0);
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signal avai_paths : std_logic_vector(TOT_NUM_PATHS-1 downto 0);
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signal arb_complete : std_logic_vector(TOT_NUM_PATHS-1 downto 0);
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signal packet_states : t_PACKET_STATES(TOT_NUM_PATHS-1 downto 0);
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@ -58,8 +64,23 @@ begin
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F_PTR_SIZE => fifo_ptr_size)
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port map(arstN => arstN, clk => clk, wr_req => snd_buff_wr_in(i).wr_req,
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rd_req => snd_buff_rd_in(i), data_in => snd_buff_wr_in(i).data,
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data_out => snd_buff_out_nxt(i).data,
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full => snd_buff_out_nxt(i).full, empty => snd_buff_out_nxt(i).empty);
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data_out => snd_buff_out(i).data,
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full => snd_buff_out(i).full, empty => snd_buff_out(i).empty);
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end generate;
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g_SENDER_GEN: for i in 0 to TOT_NUM_PATHS-1 generate
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output_sender: sender
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port map(clk => clk, send_req => snd_data_rd_reqs(i),
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ack => send_ack(i), data_in => snd_buff_out(i).data,
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req => send_reqs(i), rd_req => snd_buff_rd_in(i),
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data => data_out(i));
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end generate;
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g_RECEIVER_GEN: for i in 0 to TOT_NUM_PATHS-1 generate
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output_receiver: receiver
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port map(clk => clk, req => rcv_reqs(i), accept_ack => rcv_accept_ack(i),
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data => data_in(i), req_flag => rcv_buff_wr_in(i).wr_req,
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ack => rcv_acks(i), data_out => rcv_buff_wr_in(i).data);
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end generate;
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arbiter0: arbiter
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@ -78,10 +99,18 @@ begin
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buff_wr_in => snd_buff_wr_in
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);
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set_avai_paths: process(snd_buff_out_nxt)
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set_rcv_accept_ack: process(rcv_buff_wr_in)
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begin
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for i in 0 to TOT_NUM_PATHS-1 loop
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avai_paths(i) <= not snd_buff_out_nxt(i).full;
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rcv_accept_ack(i) <= not rcv_buff_out(i).full;
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end loop;
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end process;
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set_avai_paths: process(snd_buff_out)
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begin
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for i in 0 to TOT_NUM_PATHS-1 loop
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avai_paths(i) <= not snd_buff_out(i).full;
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snd_data_rd_reqs(i) <= not snd_buff_out(i).empty;
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end loop;
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end process;
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@ -136,7 +165,7 @@ begin
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end loop;
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end process;
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update_signals: process(arstN, clk)
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update_regs: process(arstN, clk)
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begin
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if arstN = '0' then
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rout_pos.chip_x <= chip_x;
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@ -148,7 +177,6 @@ begin
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packet_states <= (others => Idle);
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rd_data <= (others => (others => '0'));
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elsif rising_edge(clk) then
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snd_buff_out <= snd_buff_out_nxt;
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packet_states <= packet_states_nxt;
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rd_data <= rd_data_nxt;
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end if;
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@ -18,6 +18,24 @@ package router_components is
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);
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end component fifo;
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component Sender is
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port (
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clk, send_req, ack : in std_logic;
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data_in : in std_logic_vector(63 downto 0);
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req, rd_req : out std_logic;
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data : out std_logic_vector(63 downto 0)
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);
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end component Sender;
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component Receiver is
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port (
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clk, req, accept_ack : in std_logic;
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data : in std_logic_vector(63 downto 0);
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req_flag, ack : out std_logic;
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data_out : out std_logic_vector(63 downto 0)
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);
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end component Receiver;
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component arbiter is
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generic(
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level : integer := 1;
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@ -32,7 +50,7 @@ package router_components is
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num_paths_up+num_paths_down*4-1 downto 0);
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arb_complete : out std_logic_vector(
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num_paths_up+num_paths_down*4-1 downto 0);
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buff_wr_in : out t_PORT_WR_IN(
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buff_wr_in : out t_FIFO_WR_INS(
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num_paths_up+num_paths_down*4-1 downto 0)
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);
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end component arbiter;
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@ -9,7 +9,7 @@ package router_types is
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constant NUM_DIRS : integer := 5;
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constant DEST_ADDR_SIZE : integer := 5;
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constant CHIP_ADDR_SIZE : integer := 5; -- *
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constant MAX_PATHS_SIZE : integer := 48;
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constant MAX_PATHS_SIZE : integer := 96;
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subtype WORD is std_logic_vector(63 downto 0);
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type t_PACKET_STATE is (Idle, Arbitration, InArbQueue);
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@ -41,11 +41,11 @@ package router_types is
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copy_y : std_logic_vector(DEST_ADDR_SIZE-1 downto 0);
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end record;
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type t_PORT_WR_IN is array (integer range <>) of t_fifo_wr_in;
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type t_PORT_RD_IN is array (integer range <>) of std_logic; -- rd_req
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type t_PORT_OUT is array (integer range <>) of t_fifo_out;
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type t_DATA is array (integer range <>) of WORD;
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type t_DATA_DIRS is array (integer range <>) of
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type t_FIFO_WR_INS is array (integer range <>) of t_fifo_wr_in;
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type t_FIFO_RD_INS is array (integer range <>) of std_logic; -- rd_req
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type t_FIFO_OUTS is array (integer range <>) of t_fifo_out;
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type t_DATA is array (integer range <>) of WORD;
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type t_DATA_DIRS is array (integer range <>) of
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std_logic_vector(NUM_DIRS-1 downto 0);
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end package;
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@ -39,18 +39,23 @@ package body routing_functions is
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copy_y := pack_dest.copy_y(level-1);
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is_other_chip := pack_dest.chip_x /= rout_pos.chip_x or
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pack_dest.chip_y /= rout_pos.chip_y;
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is_cousin_core := (pack_dest.core_x(DEST_ADDR_SIZE-1 downto level) /=
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rout_pos.core_x(DEST_ADDR_SIZE-1 downto level)) or
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(pack_dest.core_y(DEST_ADDR_SIZE-1 downto level) /=
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rout_pos.core_y(DEST_ADDR_SIZE-1 downto level));
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--pack_dest.core_x(DEST_ADDR_SIZE-1 downto level) /= rout_pos.core_x or
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--pack_dest.core_y(DEST_ADDR_SIZE-1 downto level) /= rout_pos.core_y;
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if level /=5 then
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is_cousin_core := (pack_dest.core_x(DEST_ADDR_SIZE-1 downto level) /=
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rout_pos.core_x(DEST_ADDR_SIZE-1 downto level)) or
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(pack_dest.core_y(DEST_ADDR_SIZE-1 downto level) /=
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rout_pos.core_y(DEST_ADDR_SIZE-1 downto level));
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--pack_dest.core_x(DEST_ADDR_SIZE-1 downto level) /= rout_pos.core_x or
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--pack_dest.core_y(DEST_ADDR_SIZE-1 downto level) /= rout_pos.core_y;
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else
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is_cousin_core := FALSE;
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end if;
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needs_multicast := FALSE;
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for i in level to DEST_ADDR_SIZE-1 loop
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needs_multicast := needs_multicast or (pack_dest.copy_x(i) = '1') or
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(pack_dest.copy_y(i) = '1');
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end loop;
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-- if it comes from upstream, it shouldn't go back to upstream
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if (not is_upstream) and (is_other_chip or is_cousin_core or needs_multicast) then
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return "10000";
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elsif copy_x = '0' and copy_y = '0' then --unicast
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39
sender.vhdl
Normal file
39
sender.vhdl
Normal file
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@ -0,0 +1,39 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity Sender is
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port (
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clk, send_req, ack : in std_logic;
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data_in : in std_logic_vector(63 downto 0);
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req, rd_req : out std_logic;
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data : out std_logic_vector(63 downto 0)
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);
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end Sender;
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architecture impl of Sender is
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signal ack1, ack2, ack3, req_nxt : std_logic;
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signal req_mux, upd_req, upd_req_nxt : std_logic;
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signal ack_edge, data_nxt_mux : std_logic;
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signal data_nxt : std_logic_vector(63 downto 0);
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begin
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upd_req_nxt <= '0' when upd_req = '1' else '1'
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when ack_edge = '1' else upd_req;
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data_nxt_mux <= '1' when upd_req = '1' and send_req = '1' else '0';
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req_nxt <= not req when data_nxt_mux else req;
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rd_req <= data_nxt_mux;
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ack_edge <= ack2 xor ack3;
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data_nxt <= data_in when data_nxt_mux = '1' else data;
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update_regs: process(clk)
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begin
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if rising_edge(clk) then
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ack1 <= ack;
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ack2 <= ack1;
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ack3 <= ack2;
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upd_req <= upd_req_nxt;
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req <= req_nxt;
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data <= data_nxt;
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end if;
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end process;
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end impl;
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4
test/input/L1_multicastY/config.txt
Normal file
4
test/input/L1_multicastY/config.txt
Normal file
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@ -0,0 +1,4 @@
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0000000000 # corex|corey
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1 # level
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1 # num path down
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2 # num path up
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@ -1,11 +1,11 @@
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10001000000000010101101011001010001000000000000000000000000000011 # U
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00000000000000000000000000000000000000000000000000000000000000000
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00000000000000000000000000000000000000000000000000000000000000000
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00000000000000000000000000000000000000000000000000000000000000000
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10001000000000010101101011001010001000000000000000000000000000011 # copy Y, dest 1- -> DS3, DS4
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00000000000000000000000000000000000000000000000000000000000000000
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00000000000000000000000000000000000000000000000000000000000000000
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||||
00000000000000000000000000000000000000000000000000000000000000000
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||||
10001000000000010101101011001010001000000000000000000000000000011
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||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00001000000000010101101011001010001000000000000000000000000000011
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
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00000000000000000000000000000000000000000000000000000000000000000
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||||
00000000000000000000000000000000000000000000000000000000000000000
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||||
|
|
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4
test/input/L1_unicast/config.txt
Normal file
4
test/input/L1_unicast/config.txt
Normal file
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@ -0,0 +1,4 @@
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0000000000 # corex|corey
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1 # level
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1 # num path down
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2 # num path up
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@ -4,5 +4,5 @@
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0001000000000000000000000000000000000000000000000000000000000111
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||||
0001000001000010001000010000000000000000000000000000000000000100
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0001000001000010001000010000000000000000000000000000000000001000
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0001000001000010001000010000000000000000000000000000000000000110
|
||||
0001000001000010001000010000000000000000000000000000000000001010
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0001000001000010001000010000000000000000000000000000000000001010
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0001000001000010001000010000000000000000000000000000000000000110
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@ -1,16 +1,16 @@
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10001000000000000001000010000000000000000000000000000000000000011 # DS1
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10001000000000000001000010000000000000000000000000000000000000011 # DS4
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00000000000000000000000000000000000000000000000000000000000000000
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10001000001000010001000010000000000000000000000000000000000000100 # U
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00000000000000000000000000000000000000000000000000000000000000000
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10001000000000000000000010000000000000000000000000000000000000101 # DS3
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10001000001000010001000010000000000000000000000000000000000000110 # U
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10001000000000000000000000000000000000000000000000000000000000111 # DS4
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00000000000000000000000000000000000000000000000000000000000000000
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10001000000000000000000010000000000000000000000000000000000000101 # DS2
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10001000000000000000000000000000000000000000000000000000000000111 # DS1
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10001000001000010001000010000000000000000000000000000000000001000 # U
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00000000000000000000000000000000000000000000000000000000000000000
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10001000000000000001000000000000000000000000000000000000000001001 # DS2
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10001000001000010001000010000000000000000000000000000000000001010 # U
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00000000000000000000000000000000000000000000000000000000000000000
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10001000000000000001000000000000000000000000000000000000000001001 # DS3
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00000000000000000000000000000000000000000000000000000000000000000
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00000000000000000000000000000000000000000000000000000000000000000
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00000000000000000000000000000000000000000000000000000000000000000
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00000000000000000000000000000000000000000000000000000000000000000
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|
|
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4
test/input/L2_multicastX/config.txt
Normal file
4
test/input/L2_multicastX/config.txt
Normal file
|
|
@ -0,0 +1,4 @@
|
|||
101--101-- # corex|corey
|
||||
2 # level
|
||||
2 # num path down
|
||||
4 # num path up
|
||||
4
test/input/L2_multicastX/result.ref
Normal file
4
test/input/L2_multicastX/result.ref
Normal file
|
|
@ -0,0 +1,4 @@
|
|||
0001000000000010101101011001010001000000000000000000000000000011
|
||||
0001000000000010101101011001010001000000000000000000000000000011
|
||||
0001000001000010001000010000000000000000000000000000000000000111
|
||||
0001000001000010001000010000000000000000000000000000000000000101
|
||||
24
test/input/L2_multicastX/stimuli.txt
Normal file
24
test/input/L2_multicastX/stimuli.txt
Normal file
|
|
@ -0,0 +1,24 @@
|
|||
10001000001000010001000010000000000000000000000000000000000000111 # U
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
10001000001000010001000010000000000000000000000000000000000000101 # U
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
10001000000000010101101011001010001000000000000000000000000000011 # copy X, dest -0 -> DS1, DS3
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000 # Router L2 000--,000--
|
||||
4
test/input/L2_unicast/config.txt
Normal file
4
test/input/L2_unicast/config.txt
Normal file
|
|
@ -0,0 +1,4 @@
|
|||
000--000-- # corex|corey
|
||||
2 # level
|
||||
2 # num path down
|
||||
4 # num path up
|
||||
14
test/input/L2_unicast/result.ref
Normal file
14
test/input/L2_unicast/result.ref
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
0001000000000000011000110000000000000000000000000000000000000011
|
||||
0001000000000000011000110000000000000000000000000000000000001010
|
||||
0001000000000000011000000000000000000000000000000000000000001001
|
||||
0001000000000000011000000000000000000000000000000000000000010000
|
||||
0001000000000000000000110000000000000000000000000000000000001000
|
||||
0001000000000000000000110000000000000000000000000000000000001111
|
||||
0001000000000000000000000000000000000000000000000000000000000110
|
||||
0001000000000000000000000000000000000000000000000000000000001101
|
||||
0001000001000010001000010000000000000000000000000000000000000100
|
||||
0001000001000010001000010000000000000000000000000000000000001011
|
||||
0001000001000010001000010000000000000000000000000000000000001110
|
||||
0001000001000010001000010000000000000000000000000000000000000101
|
||||
0001000001000010001000010000000000000000000000000000000000001100
|
||||
0001000001000010001000010000000000000000000000000000000000000111
|
||||
36
test/input/L2_unicast/stimuli.txt
Normal file
36
test/input/L2_unicast/stimuli.txt
Normal file
|
|
@ -0,0 +1,36 @@
|
|||
10001000000000000011000110000000000000000000000000000000000000011 # DS4
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
10001000001000010001000010000000000000000000000000000000000000100 # U
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
10001000001000010001000010000000000000000000000000000000000000101 # U
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
10001000001000010001000010000000000000000000000000000000000000111 # U
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
10001000000000000000000000000000000000000000000000000000000000110 # DS1
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
10001000000000000000000110000000000000000000000000000000000001000 # DS2
|
||||
10001000000000000011000000000000000000000000000000000000000001001 # DS3
|
||||
10001000001000010001000010000000000000000000000000000000000001011 # U
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
10001000001000010001000010000000000000000000000000000000000001100 # U
|
||||
10001000000000000011000110000000000000000000000000000000000001010 # DS4
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
10001000001000010001000010000000000000000000000000000000000001110 # U
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
10001000000000000000000000000000000000000000000000000000000001101 # DS1
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
10001000000000000000000110000000000000000000000000000000000001111 # DS2
|
||||
10001000000000000011000000000000000000000000000000000000000010000 # DS3
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000 # Router L2 000--,000--
|
||||
4
test/input/L5_multicast4/config.txt
Normal file
4
test/input/L5_multicast4/config.txt
Normal file
|
|
@ -0,0 +1,4 @@
|
|||
---------- # corex|corey
|
||||
5 # level
|
||||
16 # num path down
|
||||
32 # num path up
|
||||
4
test/input/L5_multicast4/result.ref
Normal file
4
test/input/L5_multicast4/result.ref
Normal file
|
|
@ -0,0 +1,4 @@
|
|||
0001000000000010101101011001010001000000000000000000000000000011
|
||||
0001000000000010101101011001010001000000000000000000000000000011
|
||||
0001000000000010101101011001010001000000000000000000000000000011
|
||||
0001000000000010101101011001010001000000000000000000000000000011
|
||||
192
test/input/L5_multicast4/stimuli.txt
Normal file
192
test/input/L5_multicast4/stimuli.txt
Normal file
|
|
@ -0,0 +1,192 @@
|
|||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
10001000000000010101101011001010001000000000000000000000000000011 # copy 4x, dest -- -> DS1, DS2, DS3, DS4
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
00000000000000000000000000000000000000000000000000000000000000000
|
||||
|
|
@ -5,6 +5,11 @@ use work.router_types.all;
|
|||
use ieee.std_logic_textio.all;
|
||||
use std.textio.all;
|
||||
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity router_tb is
|
||||
end;
|
||||
|
||||
|
|
@ -17,18 +22,23 @@ architecture bench of router_tb is
|
|||
constant level : integer := 1;
|
||||
constant buffer_width : integer := 64;
|
||||
constant buffer_depth : integer := 4;
|
||||
constant fifo_ptr_size: integer := 3;
|
||||
constant fifo_ptr_size : integer := 3;
|
||||
constant chip_x : std_logic_vector(4 downto 0) := (others => '0');
|
||||
constant chip_y : std_logic_vector(4 downto 0) := (others => '0');
|
||||
constant core_x : std_logic_vector(4 downto 0) := "0010-";
|
||||
constant core_y : std_logic_vector(4 downto 0) := "0010-";
|
||||
constant core_x : std_logic_vector(4 downto 0) := (others => '0');
|
||||
constant core_y : std_logic_vector(4 downto 0) := (others => '0');
|
||||
-- Ports
|
||||
signal clk : std_logic;
|
||||
signal arstN : std_logic;
|
||||
signal rcv_buff_wr_in : t_PORT_WR_IN(num_paths_up+num_paths_down*4-1 downto 0);
|
||||
signal snd_buff_rd_in : std_logic_vector(num_paths_up+num_paths_down*4-1 downto 0);
|
||||
signal snd_buff_out : t_PORT_OUT(num_paths_up+num_paths_down*4-1 downto 0);
|
||||
signal clk : std_logic;
|
||||
signal arstN : std_logic;
|
||||
signal data_in : t_DATA(num_paths_up+num_paths_down*4-1 downto 0);
|
||||
signal rcv_reqs : std_logic_vector(num_paths_up+num_paths_down*4-1 downto 0);
|
||||
signal send_ack : std_logic_vector(num_paths_up+num_paths_down*4-1 downto 0);
|
||||
signal send_ack_nxt : std_logic_vector(num_paths_up+num_paths_down*4-1 downto 0);
|
||||
signal rcv_acks : std_logic_vector(num_paths_up+num_paths_down*4-1 downto 0);
|
||||
signal send_reqs : std_logic_vector(num_paths_up+num_paths_down*4-1 downto 0);
|
||||
signal data_out : t_DATA(num_paths_up+num_paths_down*4-1 downto 0);
|
||||
|
||||
file conf_file : text open read_mode is "config.txt";
|
||||
file stimuli_file : text open read_mode is "stimuli.txt";
|
||||
file reference_file : text open read_mode is "result.ref";
|
||||
file log_file : text open write_mode is "simulation.log";
|
||||
|
|
@ -50,11 +60,13 @@ begin
|
|||
port map (
|
||||
clk => clk,
|
||||
arstN => arstN,
|
||||
rcv_buff_wr_in => rcv_buff_wr_in,
|
||||
snd_buff_rd_in => snd_buff_rd_in,
|
||||
snd_buff_out => snd_buff_out
|
||||
data_in => data_in,
|
||||
rcv_reqs => rcv_reqs,
|
||||
send_ack => send_ack,
|
||||
rcv_acks => rcv_acks,
|
||||
send_reqs => send_reqs,
|
||||
data_out => data_out
|
||||
);
|
||||
-- clk <= not clk after clk_period/2;
|
||||
|
||||
clock_gen: process
|
||||
begin
|
||||
|
|
@ -68,13 +80,10 @@ begin
|
|||
variable input_line, rowOut : line;
|
||||
variable valid_data : boolean;
|
||||
variable stimuli : std_logic_vector(64 downto 0);
|
||||
variable istwert, sollwert : WORD;
|
||||
variable index_path : integer;
|
||||
variable test_passed : boolean;
|
||||
begin
|
||||
test_passed := TRUE;
|
||||
arstN <= '0';
|
||||
snd_buff_rd_in <= (others => '0');
|
||||
rcv_reqs <= (others => '0');
|
||||
wait until rising_edge(clk);
|
||||
-- writing and arbitration
|
||||
arstN <= '1';
|
||||
|
|
@ -84,29 +93,33 @@ begin
|
|||
read(input_line, stimuli, valid_data);
|
||||
assert valid_data
|
||||
report "Invalid data in file" severity error;
|
||||
rcv_buff_wr_in(index_path).data <= stimuli(63 downto 0);
|
||||
rcv_buff_wr_in(index_path).wr_req <= stimuli(64);
|
||||
data_in(index_path) <= stimuli(63 downto 0);
|
||||
rcv_reqs(index_path) <= stimuli(64);
|
||||
index_path := index_path + 1;
|
||||
if index_path = num_paths_down*4 + num_paths_up then
|
||||
wait until rising_edge(clk);
|
||||
wait until rcv_acks(index_path-1)='1';
|
||||
index_path := 0;
|
||||
end if;
|
||||
exit when endfile(stimuli_file);
|
||||
end loop;
|
||||
wait until rising_edge(clk);
|
||||
wait for clk_period*5;
|
||||
wait;
|
||||
end process;
|
||||
|
||||
-- reading from send fifo and validating
|
||||
wait until rising_edge(clk);
|
||||
validate_routed_data: process(send_reqs, data_out, send_ack)
|
||||
variable input_line, rowOut : line;
|
||||
variable valid_data : boolean;
|
||||
variable confi : std_logic_vector(9 downto 0);
|
||||
variable istwert, sollwert : WORD;
|
||||
variable test_passed : boolean;
|
||||
begin
|
||||
test_passed := TRUE;
|
||||
for i in 0 to num_paths_down*4+num_paths_up-1 loop
|
||||
while snd_buff_out(i).empty = '0' loop
|
||||
istwert := snd_buff_out(i).data;
|
||||
snd_buff_rd_in(i) <= '1';
|
||||
wait until rising_edge(clk);
|
||||
snd_buff_rd_in(i) <= '0';
|
||||
wait until rising_edge(clk);
|
||||
wait until rising_edge(clk);
|
||||
wait until rising_edge(clk);
|
||||
if send_ack(i) = '1' then
|
||||
send_ack_nxt(i) <= '0';
|
||||
elsif send_reqs(i) = '1' then
|
||||
istwert := data_out(i);
|
||||
send_ack_nxt(i) <= '1';
|
||||
readline(reference_file, input_line);
|
||||
read(input_line, sollwert, valid_data);
|
||||
assert valid_data report "Invalid data in file" severity error;
|
||||
|
|
@ -133,21 +146,26 @@ begin
|
|||
WRITELINE(log_file, rowOut);
|
||||
test_passed := test_passed and FALSE;
|
||||
end if;
|
||||
exit when endfile(reference_file);
|
||||
end loop;
|
||||
else
|
||||
send_ack_nxt(i) <= '0';
|
||||
end if;
|
||||
exit when endfile(reference_file);
|
||||
end loop;
|
||||
wait until rising_edge(clk);
|
||||
if not endfile(reference_file) then
|
||||
test_passed := FALSE;
|
||||
if endfile(reference_file) then
|
||||
if test_passed then
|
||||
write(rowOut, string'("All tests passed successfully!"));
|
||||
WRITELINE(log_file, rowOut);
|
||||
else
|
||||
write(rowOut, string'("One or more tests failed"));
|
||||
WRITELINE(log_file, rowOut);
|
||||
end if;
|
||||
end if;
|
||||
if test_passed then
|
||||
write(rowOut, string'("All tests passed successfully!"));
|
||||
WRITELINE(log_file, rowOut);
|
||||
else
|
||||
write(rowOut, string'("One or more tests failed"));
|
||||
WRITELINE(log_file, rowOut);
|
||||
end if;
|
||||
wait;
|
||||
end process;
|
||||
end architecture;
|
||||
|
||||
update_signals: process(clk)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
send_ack <= send_ack_nxt;
|
||||
end if;
|
||||
end process;
|
||||
end;
|
||||
|
|
|
|||
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Add table
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Reference in a new issue