55 lines
No EOL
1.4 KiB
VHDL
55 lines
No EOL
1.4 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity encoder16to4 is
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port (
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din : in STD_LOGIC_VECTOR(15 downto 0);
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dout : out STD_LOGIC_VECTOR(3 downto 0);
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valid : out STD_LOGIC -- '1' if any input is high, '0' if all zero
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);
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end encoder16to4;
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architecture impl of encoder16to4 is
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begin
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process(din)
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begin
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valid <= '1';
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if din(15) = '1' then
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dout <= "1111";
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elsif din(14) = '1' then
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dout <= "1110";
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elsif din(13) = '1' then
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dout <= "1101";
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elsif din(12) = '1' then
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dout <= "1100";
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elsif din(11) = '1' then
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dout <= "1011";
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elsif din(10) = '1' then
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dout <= "1010";
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elsif din(9) = '1' then
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dout <= "1001";
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elsif din(8) = '1' then
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dout <= "1000";
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elsif din(7) = '1' then
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dout <= "0111";
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elsif din(6) = '1' then
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dout <= "0110";
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elsif din(5) = '1' then
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dout <= "0101";
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elsif din(4) = '1' then
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dout <= "0100";
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elsif din(3) = '1' then
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dout <= "0011";
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elsif din(2) = '1' then
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dout <= "0010";
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elsif din(1) = '1' then
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dout <= "0001";
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elsif din(0) = '1' then
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dout <= "0000";
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else
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dout <= "0000";
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valid <= '0';
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end if;
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end process;
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end impl; |