33 lines
No EOL
948 B
VHDL
33 lines
No EOL
948 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.encoder_components.all;
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entity encoder_generic is
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generic(
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din_size : natural
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);
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port (
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din : in STD_LOGIC_VECTOR(din_size-1 downto 0);
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dout : out STD_LOGIC_VECTOR(get_dout_size(din_size)-1 downto 0);
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valid : out STD_LOGIC -- '1' if any input is high, '0' if all zero
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);
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end encoder_generic;
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architecture impl of encoder_generic is
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begin
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g_32_encoder: if din_size = 32 generate
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encoder32: encoder32to5
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port map (din => din, dout => dout, valid => valid);
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end generate;
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g_16_encoder: if din_size = 16 generate
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encoder16: encoder16to4
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port map (din => din, dout => dout, valid => valid);
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end generate;
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g_8_encoder: if din_size = 8 generate
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encoder8: encoder8to3
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port map (din => din, dout => dout, valid => valid);
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end generate;
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end impl; |