109 lines
No EOL
5.2 KiB
VHDL
109 lines
No EOL
5.2 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.router_types.all;
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use work.quadtree_components.all;
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use work.noc_conf.all;
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entity noc is
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generic (
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num_paths_ext : positive := 32;
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buffer_width : positive := 64;
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buffer_depth : positive := 4;
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fifo_ptr_size : positive := 3;
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level : positive := 5;
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top_level : positive := 5;
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chip_x : std_logic_vector(4 downto 0) := "00000";
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chip_y : std_logic_vector(4 downto 0) := "00000"
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);
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port (
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clks : in std_logic_vector(
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calculate_num_routers(top_level)-1 downto 0);
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arstN : in std_logic;
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data_chip_in : in t_DATA_EXT(4*num_paths_ext-1 downto 0);
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c_rcv_reqs : in std_logic_vector(4*num_paths_ext-1 downto 0);
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c_send_ack : in std_logic_vector(4*num_paths_ext-1 downto 0);
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pe_data_in : in t_DATA(4**level-1 downto 0);
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pe_rcv_reqs : in std_logic_vector(4**level-1 downto 0);
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pe_send_ack : in std_logic_vector(4**level-1 downto 0);
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data_chip_out : out t_DATA_EXT(4*num_paths_ext-1 downto 0);
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c_rcv_ack : out std_logic_vector(4*num_paths_ext-1 downto 0);
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c_send_reqs : out std_logic_vector(4*num_paths_ext-1 downto 0);
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pe_data_out : out t_DATA(4**level-1 downto 0);
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pe_rcv_acks : out std_logic_vector(4**level-1 downto 0);
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pe_send_reqs : out std_logic_vector(4**level-1 downto 0)
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);
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end noc;
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architecture impl of noc is
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constant l5_core_x : std_logic_vector(4 downto 0) := "00000";
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constant l5_core_y : std_logic_vector(4 downto 0) := "00000";
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constant num_paths_up : positive := 32;
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constant num_paths_down : positive := 16;
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constant npu_bit_size : positive := 6;
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constant npd_bit_size : positive := 5;
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constant num_routers : integer := calculate_num_routers(top_level);
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signal r_data_ds_in : t_DATA(4*num_paths_down-1 downto 0);
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signal r_data_ds_out : t_DATA(4*num_paths_down-1 downto 0);
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signal r_rcv_reqs : std_logic_vector(4*num_paths_up+4*num_paths_down-1 downto 0);
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signal r_rcv_reqs_ds : std_logic_vector(4*num_paths_down-1 downto 0);
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signal r_snd_ack : std_logic_vector(4*num_paths_up+4*num_paths_down-1 downto 0);
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signal r_snd_ack_ds : std_logic_vector(4*num_paths_down-1 downto 0);
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signal r_snd_reqs : std_logic_vector(4*num_paths_up+4*num_paths_down-1 downto 0);
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signal r_snd_reqs_ds : std_logic_vector(4*num_paths_down-1 downto 0);
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signal r_rcv_ack : std_logic_vector(4*num_paths_up+4*num_paths_down-1 downto 0);
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signal r_rcv_ack_ds : std_logic_vector(4*num_paths_down-1 downto 0);
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signal s_data_chip_out : t_DATA_EXT(4*num_paths_ext-1 downto 0);
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signal s_c_rcv_ack : std_logic_vector(4*num_paths_ext-1 downto 0);
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signal s_c_send_reqs : std_logic_vector(4*num_paths_ext-1 downto 0);
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begin
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r_rcv_reqs <= c_rcv_reqs & r_rcv_reqs_ds;
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r_snd_ack <= c_send_ack & r_snd_ack_ds;
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s_c_send_reqs <= r_snd_reqs(4*num_paths_up+4*num_paths_down-1 downto 4*num_paths_down);
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r_snd_reqs_ds <= r_snd_reqs(4*num_paths_down-1 downto 0);
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s_c_rcv_ack <= r_rcv_ack(4*num_paths_up+4*num_paths_down-1 downto 4*num_paths_down);
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r_rcv_ack_ds <= r_rcv_ack(4*num_paths_down-1 downto 0);
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c_send_reqs <= s_c_send_reqs;
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c_rcv_ack <= s_c_rcv_ack;
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data_chip_out <= s_data_chip_out;
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router_l5: parent_router
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generic map(num_paths_up => num_paths_up, num_paths_down => num_paths_down,
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npu_bit_size => npu_bit_size, npd_bit_size => npd_bit_size,
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level => level, buffer_width => buffer_width, buffer_depth => buffer_depth,
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fifo_ptr_size => fifo_ptr_size, chip_x => chip_x, chip_y => chip_y)
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port map(clk => clks(num_routers-1), arstN => arstN, core_x => l5_core_x, core_y => l5_core_y,
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data_in_ds => r_data_ds_in, data_in_us => data_chip_in,
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rcv_reqs => r_rcv_reqs, send_ack => r_snd_ack, rcv_acks => r_rcv_ack,
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send_reqs => r_snd_reqs, data_out_ds => r_data_ds_out,
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data_out_us => s_data_chip_out);
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quadtree_inst: quadtree
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generic map(num_paths_up => num_paths_up, num_paths_down => num_paths_down,
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npu_bit_size => npu_bit_size, npd_bit_size => npd_bit_size,
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level => level, top_level => top_level,
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buffer_width => buffer_width, buffer_depth => buffer_depth,
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fifo_ptr_size => fifo_ptr_size, chip_x => chip_x, chip_y => chip_y)
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port map(clks => clks(num_routers-2 downto 0),
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arstN => arstN, core_x => l5_core_x,
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core_y => l5_core_y, data_in_us => r_data_ds_out,
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rcv_reqs_us => r_snd_reqs_ds, send_ack_us => r_rcv_ack_ds,
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pe_data_in => pe_data_in, pe_rcv_reqs => pe_rcv_reqs,
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pe_send_ack => pe_send_ack, data_out_us => r_data_ds_in,
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rcv_acks_us => r_snd_ack_ds, send_reqs_us => r_rcv_reqs_ds,
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pe_rcv_acks => pe_rcv_acks, pe_send_reqs => pe_send_reqs,
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pe_data_out => pe_data_out);
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end impl; |