76 lines
No EOL
3.3 KiB
VHDL
76 lines
No EOL
3.3 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.router_types.all;
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use work.quadtree_components.all;
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package noc_conf is
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component parent_router is
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generic (
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num_paths_up : positive := 32;
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num_paths_down : positive := 16;
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npu_bit_size : positive := 5;
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npd_bit_size : positive := 4;
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level : natural := 5;
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buffer_width : positive := 64;
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buffer_depth : positive := 4;
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fifo_ptr_size : positive := 3;
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chip_x : std_logic_vector(4 downto 0);
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chip_y : std_logic_vector(4 downto 0)
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);
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port (
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clk : in std_logic;
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arstN : in std_logic;
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core_x : in std_logic_vector(4 downto 0);
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core_y : in std_logic_vector(4 downto 0);
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data_in_ds : in t_DATA(num_paths_down*4-1 downto 0);
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data_in_us : in t_DATA_EXT(num_paths_up*4-1 downto 0);
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rcv_reqs : in std_logic_vector(num_paths_up*4+num_paths_down*4-1 downto 0);
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send_ack : in std_logic_vector(num_paths_up*4+num_paths_down*4-1 downto 0);
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rcv_acks : out std_logic_vector(num_paths_up*4+num_paths_down*4-1 downto 0);
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send_reqs : out std_logic_vector(num_paths_up*4+num_paths_down*4-1 downto 0);
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data_out_ds : out t_DATA(num_paths_down*4-1 downto 0);
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data_out_us : out t_DATA_EXT(num_paths_up*4-1 downto 0)
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);
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end component parent_router;
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component quadtree is
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generic (
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num_paths_up : positive := 32;
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num_paths_down : positive := 16;
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npu_bit_size : positive := 5;
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npd_bit_size : positive := 4;
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buffer_width : positive := 64;
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buffer_depth : positive := 4;
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fifo_ptr_size : positive := 3;
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level : natural := 5;
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top_level : positive := 5;
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chip_x : std_logic_vector(4 downto 0) := "00000";
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chip_y : std_logic_vector(4 downto 0) := "00000"
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);
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port (
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clks : in std_logic_vector(
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calculate_num_routers_qt(level, top_level)-1 downto 0);
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arstN : in std_logic;
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core_x : in std_logic_vector(4 downto 0);
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core_y : in std_logic_vector(4 downto 0);
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data_in_us : in t_DATA(4*num_paths_up/2-1 downto 0);
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rcv_reqs_us : in std_logic_vector(4*num_paths_up/2-1 downto 0);
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send_ack_us : in std_logic_vector(4*num_paths_up/2-1 downto 0);
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pe_data_in : in t_DATA(4**level-1 downto 0);
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pe_rcv_reqs : in std_logic_vector(4**level-1 downto 0);
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pe_send_ack : in std_logic_vector(4**level-1 downto 0);
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data_out_us : out t_DATA(4*num_paths_up/2-1 downto 0);
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rcv_acks_us : out std_logic_vector(4*num_paths_up/2-1 downto 0);
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send_reqs_us : out std_logic_vector(4*num_paths_up/2-1 downto 0);
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pe_rcv_acks : out std_logic_vector(4**level-1 downto 0);
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pe_send_reqs : out std_logic_vector(4**level-1 downto 0);
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pe_data_out : out t_DATA(4**level-1 downto 0)
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);
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end component;
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end package; |