47 lines
No EOL
1.6 KiB
VHDL
47 lines
No EOL
1.6 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity Receiver is
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port (
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clk, req, arstN, accept_ack : in std_logic;
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data : in std_logic_vector(63 downto 0);
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req_flag, ack : out std_logic;
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data_out : out std_logic_vector(63 downto 0)
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);
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end Receiver;
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architecture impl of Receiver is
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signal req1, req2, req3 : std_logic;
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signal req_edge, upd_ack : std_logic;
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signal ack_nxt, sgn_ack : std_logic;
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signal req_flag1, req_flag2, req_flag3 : std_logic;
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signal data_nxt, sgn_data : std_logic_vector(63 downto 0);
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begin
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req_edge <= req2 xor req3;
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upd_ack <= accept_ack and req_flag2;
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req_flag1 <= '1' when req_edge = '1' else '0'
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when upd_ack = '1' else req_flag2;
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ack_nxt <= not sgn_ack when (upd_ack) = '1' else sgn_ack;
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req_flag <= req_flag3 and (not req_flag2);
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data_nxt <= data when req_edge = '1' else sgn_data;
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ack <= sgn_ack;
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data_out <= sgn_data;
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update_regs: process(clk)
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begin
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if arstN = '0' then
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sgn_ack <= '0';
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sgn_data <= (others => '0');
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elsif rising_edge(clk) then
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req1 <= req;
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req2 <= req1;
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req3 <= req2;
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req_flag2 <= req_flag1;
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req_flag3 <= req_flag2;
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sgn_ack <= ack_nxt;
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sgn_data <= data_nxt;
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end if;
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end process;
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end impl; |