82 lines
No EOL
3.2 KiB
VHDL
82 lines
No EOL
3.2 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.router_types.all;
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package router_components is
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component fifo is
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generic (
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WIDTH : positive;
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DEPTH : positive;
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F_PTR_SIZE : positive
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);
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port(
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arstN, clk, wr_req, rd_req : in std_logic;
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full, empty : out std_logic;
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data_in : in std_logic_vector(WIDTH-1 downto 0);
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data_out : out std_logic_vector(WIDTH-1 downto 0)
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);
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end component fifo;
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component Sender is
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port (
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clk, continue_send, ack, arstN : in std_logic;
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data_in : in std_logic_vector(63 downto 0);
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req, rd_req : out std_logic;
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data : out std_logic_vector(63 downto 0)
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);
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end component Sender;
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component Receiver is
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port (
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clk, req, arstN, accept_ack : in std_logic;
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data : in std_logic_vector(63 downto 0);
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req_flag, ack : out std_logic;
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data_out : out std_logic_vector(63 downto 0)
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);
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end component Receiver;
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component arbiter is
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generic(
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level : natural := 1;
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num_paths_up : positive := 1;
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num_paths_down : positive := 1;
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lsb_size_up : positive := 2;
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lsb_size_down : positive := 1
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);
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port (
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clk, arstN : in std_logic;
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chip_pos : in t_chip_addr;
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core_pos : in t_core_addr;
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packets : in t_DATA(num_paths_up+num_paths_down*4-1 downto 0);
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valid_data : in std_logic_vector(
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num_paths_up+num_paths_down*4-1 downto 0);
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avai_paths : in std_logic_vector(
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num_paths_up+num_paths_down*4-1 downto 0);
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arb_complete : out std_logic_vector(
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num_paths_up+num_paths_down*4-1 downto 0);
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buff_wr_in : out t_FIFO_WR_INS(
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num_paths_up+num_paths_down*4-1 downto 0)
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);
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end component arbiter;
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component parent_arbiter is
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generic(
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level : natural := 5;
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num_paths_up : positive := 32;
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num_paths_down : positive := 16;
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lsb_size_up : positive := 5;
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lsb_size_down : positive := 4
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);
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port (
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clk, arstN : in std_logic;
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chip_pos : in t_chip_addr;
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core_pos : in t_core_addr;
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packets : in t_DATA(num_paths_up*4+num_paths_down*4-1 downto 0);
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valid_data : in std_logic_vector(num_paths_up*4+num_paths_down*4-1 downto 0);
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avai_paths : in std_logic_vector(num_paths_up*4+num_paths_down*4-1 downto 0);
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arb_complete : out std_logic_vector(num_paths_up*4+num_paths_down*4-1 downto 0);
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buff_wr_in : out t_FIFO_WR_INS(num_paths_up*4+num_paths_down*4-1 downto 0)
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);
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end component parent_arbiter;
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end package; |