46 lines
No EOL
1.6 KiB
VHDL
46 lines
No EOL
1.6 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity Sender is
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port (
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clk, continue_send, ack, arstN : in std_logic;
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data_in : in std_logic_vector(63 downto 0);
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req, rd_req : out std_logic;
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data : out std_logic_vector(63 downto 0)
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);
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end Sender;
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architecture impl of Sender is
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signal ack1, ack2, ack3, req_nxt : std_logic;
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signal upd_req, upd_req_nxt : std_logic;
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signal sgn_req : std_logic;
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signal ack_edge, data_nxt_mux : std_logic;
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signal data_nxt, sgn_data : std_logic_vector(63 downto 0);
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begin
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upd_req_nxt <= '0' when data_nxt_mux = '1' else '1'
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when ack_edge = '1' else upd_req;
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data_nxt_mux <= '1' when upd_req = '1' and continue_send = '1' else '0';
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req_nxt <= not sgn_req when data_nxt_mux = '1' else sgn_req;
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rd_req <= ack_edge; -- means that the data has been received
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ack_edge <= ack2 xor ack3;
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data_nxt <= data_in when data_nxt_mux = '1' else sgn_data;
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req <= sgn_req;
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data <= sgn_data;
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update_regs: process(clk)
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begin
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if arstN = '0' then
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sgn_req <= '0';
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upd_req <= '1';
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sgn_data <= (others => '0');
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elsif rising_edge(clk) then
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ack1 <= ack;
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ack2 <= ack1;
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ack3 <= ack2;
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upd_req <= upd_req_nxt;
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sgn_req <= req_nxt;
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sgn_data <= data_nxt;
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end if;
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end process;
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end impl; |