74 lines
No EOL
1.5 KiB
VHDL
Executable file
74 lines
No EOL
1.5 KiB
VHDL
Executable file
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity fifo_tb is
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end;
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architecture bench of fifo_tb is
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-- Clock period
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constant clk_period : time := 5 ns;
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-- Generics
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constant WIDTH : integer := 32;
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constant DEPTH : integer := 8;
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constant F_PTR_SIZE : integer := 4;
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-- Ports
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signal arstN : std_logic;
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signal clk : std_logic;
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signal wr_req : std_logic;
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signal rd_req : std_logic;
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signal full : std_logic;
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signal empty : std_logic;
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signal data_in : std_logic_vector(WIDTH-1 downto 0);
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signal data_out : std_logic_vector(WIDTH-1 downto 0);
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begin
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fifo_inst : entity work.fifo
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generic map (
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WIDTH => WIDTH,
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DEPTH => DEPTH,
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F_PTR_SIZE => F_PTR_SIZE
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)
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port map (
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arstN => arstN,
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clk => clk,
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wr_req => wr_req,
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rd_req => rd_req,
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full => full,
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empty => empty,
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data_in => data_in,
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data_out => data_out
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);
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clock_gen: process
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begin
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clk <= '0';
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wait for clk_period/2;
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clk <= '1';
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wait for clk_period/2;
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end process;
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test: process
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begin
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arstN <= '0';
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wait for CLK_PERIOD;
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arstN <= '1';
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for value_sent in 10 downto 0 loop
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wr_req <= '1';
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data_in <= std_logic_vector(to_unsigned(value_sent, data_in'length));
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wait for clk_period;
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wr_req <= '0';
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wait for clk_period;
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end loop;
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for counter in 0 to 10 loop
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rd_req <= '1';
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wait for clk_period;
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--rd_req <= '0';
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--wait for clk_period;
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end loop;
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wait;
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end process;
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end; |