15 lines
363 B
Verilog
15 lines
363 B
Verilog
//16 bit Linear Feedback Shift Register (LFSR)
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module lfsr16 #(
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parameter DATA_WIDTH = 16
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)(
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input clk,
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input rst,
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output reg [15:0] out
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);
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always @(posedge clk or posedge rst) begin
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if (rst)
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out <= 16'h1;
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else
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out <= {out[14:0], out[15] ^ out[13] ^ out[12] ^ out[10]};
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end
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endmodule
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