227 lines
7.2 KiB
Verilog
227 lines
7.2 KiB
Verilog
`timescale 1ns / 1ps
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module tb_top_rpas #(
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// Parameters
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parameter ROWS1 = 16, // Reading matrix rows
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parameter COLS1 = 12, // Reading matrix cols
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parameter ROWS2 = 12,
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parameter COLS2 = 12,
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parameter ROWS3 = 16, // Writing matrix rows
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parameter COLS3 = 32, // Writing matrix cols
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parameter DATA_WIDTH = 16
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)();
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// === Clock and Reset ===
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reg clk = 0;
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reg rst = 1;
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always #5 clk = ~clk; // 100MHz clock (10ns period)
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// === Control Signals ===
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reg enable_rpas;
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// === Address and Size Configs ===
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reg [$clog2(ROWS1)-1:0] rows_start_add_reading, rows_start_add_writing, rows_size_reading, rows_size_writing;
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reg [$clog2(COLS1)-1:0] cols_start_add_reading, cols_size_reading; // Corrected width
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reg [$clog2(COLS3)-1:0] cols_size_writing, cols_start_add_writing;
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// === Wires for RPAS <-> Memory Connections ===
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wire [$clog2(ROWS1)-1:0] row_addr_out_read, row_addr_out_write;
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wire [$clog2(COLS1)-1:0] col_addr_out_read;
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wire [$clog2(COLS3)-1:0] col_addr_out_write;
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wire write_enable;
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wire read_enable;
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wire read_valid;
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wire valid_result;
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wire [DATA_WIDTH - 1:0] data_input_to_mem_1, data_input_to_mem_2, data_input_to_mem_3;
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wire [DATA_WIDTH - 1:0] data_output_from_mem_1, data_output_from_mem_2, data_output_from_mem_3;
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reg read_full_row_or_col1, read_full_row_or_col2, read_full_row_or_col3;
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wire [DATA_WIDTH*((ROWS1>COLS1)?ROWS1-1:COLS1-1):0] full_row_output_1; // For full row reads //COLS1
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wire [DATA_WIDTH*((ROWS2>COLS2)?ROWS2-1:COLS2-1):0] full_row_output_2; // (optional) for Matrix 2 //COLS2
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wire [DATA_WIDTH*((ROWS3>COLS3)?ROWS3-1:COLS3-1):0] full_row_output_3; // (optional) for Matrix 3 //COLS3
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reg write_back_to_file_enable; //writing enable the file back into the memory
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wire done_writing_to_file; ////writing enable the file back into the memory
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// === Instantiate top_module_mem ===
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top_module_mem #(
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.ROWS1(ROWS1),
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.COLS1(COLS1),
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.ROWS2(ROWS2),
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.COLS2(COLS2),
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.ROWS3(ROWS3),
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.COLS3(COLS3),
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.DATA_WIDTH(DATA_WIDTH)
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) u_top_mem (
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.clk(clk),
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// Memory 1
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.row_addr_1(row_addr_out_read),
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.col_addr_1(col_addr_out_read),
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.write_enable_1(),
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.read_enable_1(),
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.data_input_1(data_input_to_mem_1),
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.data_output_1(data_output_from_mem_1),
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.valid_1(read_valid),
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.read_full_row_or_col1(read_full_row_or_col1), //1'b0
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.read_full_row_1(read_enable),
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.no_cols_used1(cols_size_reading),
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.no_rows_used1(rows_size_reading),
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.full_row_output_1(full_row_output_1),
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.full_row_input_1(),
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.write_full_row_1(),////////
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//memory 2
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.row_addr_2(),
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.col_addr_2(),
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.write_enable_2(),
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.read_enable_2(),
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.data_input_2(data_input_to_mem_2),
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.valid_2(),
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.read_full_row_or_col2(read_full_row_or_col2),
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.read_full_row_2(),
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.no_cols_used2(),
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.no_rows_used2(),
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.full_row_output_2(full_row_output_2),
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.full_row_input_2(),
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.write_full_row_2(),
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//memory 3
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.row_addr_3(row_addr_out_write),
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.col_addr_3(col_addr_out_write),
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.write_enable_3(write_enable),
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.read_enable_3(),
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.data_input_3(data_input_to_mem_3),
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.data_output_3(data_output_from_mem_3),
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.valid_3(),
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.read_full_row_or_col3(read_full_row_or_col3),//////1'b0
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.read_full_row_3(),
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.no_cols_used3(cols_size_writing),///
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.no_rows_used3(rows_size_writing),///
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.full_row_output_3(full_row_output_3),
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.full_row_input_3(),
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.write_full_row_3(),
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.write_back_to_file_enable(write_back_to_file_enable),
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.done_writing_to_file(done_writing_to_file)
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);
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// === Instantiate top_module_rpas ===
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top_module_rpas #(
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.ROWS_READING(ROWS1),
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.COLS_READING(COLS1),
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.ROWS_WRITING(ROWS3),
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.COLS_WRITING(COLS3),
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.DATA_WIDTH(DATA_WIDTH)
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) u_rpas (
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.clk(clk),
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.rst(rst),
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.enable_rpas(enable_rpas),
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.read_valid(read_valid),
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.rows_start_add_reading(rows_start_add_reading),
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.cols_start_add_reading(cols_start_add_reading),
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.rows_start_add_writing(rows_start_add_writing),
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.cols_start_add_writing(cols_start_add_writing),
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.rows_size_reading(rows_size_reading),
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.cols_size_reading(cols_size_reading),
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.rows_size_writing(rows_size_writing),
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.cols_size_writing(cols_size_writing),
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// .data_input(data_output_from_mem_1),
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.data_input_rows(full_row_output_1),
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.row_addr_out_read(row_addr_out_read),
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.col_addr_out_read(col_addr_out_read),
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.row_addr_out_write(row_addr_out_write),
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.col_addr_out_write(col_addr_out_write),
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.data_output(data_input_to_mem_3),
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.write_enable(write_enable),
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.read_enable_full_row(read_enable),
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.valid_result(valid_result)
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);
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// === Test Sequence ===
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initial begin
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$display("=== RPAS Testbench Starting (1/2)===");
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// Initial states
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read_full_row_or_col1 = 0;//0 to read row wise & 1 to read col wise
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read_full_row_or_col3 = 1;//0 to read row wise & 1 to read col wise
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enable_rpas = 0;
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// Reset sequence
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#20;
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rst = 0;
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// Enable the RPAS unit
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#10;
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enable_rpas = 1;
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// Set read and write offsets and sizes
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rows_start_add_reading <= 4'b0;
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cols_start_add_reading <= 4'b0;
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rows_start_add_writing <= 4'b0;
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cols_start_add_writing <= 5'b0;
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rows_size_reading <= 4'd15; // 0 to 15
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cols_size_reading <= 4'd11; // 0 to 11
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rows_size_writing <= 4'd15; // 0 to 15
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cols_size_writing <= 5'd31; // 0 to 31
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// Wait for result
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wait (valid_result);
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#50;
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$display("=== RPAS Testbench Completed (1/2)===");
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#10
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/*
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$display("=== RPAS Testbench Starting (2/2)===");
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// Initial states
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enable_rpas = 0;
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rst = 1;
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// Reset sequence
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#20;
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rst = 0;
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// Enable the RPAS unit
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#10;
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enable_rpas = 1;
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// Set read and write offsets and sizes
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rows_start_add_reading <= 4'b0;
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cols_start_add_reading <= 4'b0;
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rows_start_add_writing <= 4'b0;
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cols_start_add_writing <= 5'b0;
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rows_size_reading <= 4'd15; // 0 to 15
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cols_size_reading <= 4'd11; // 0 to 11
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rows_size_writing <= 4'd15; // 0 to 15
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cols_size_writing <= 5'd31; // 0 to 31
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// Wait for result
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wait (valid_result);
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#50;
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$display("=== RPAS Testbench Completed (2/2)===");
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*/
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//enable writing signal for memory dump
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write_back_to_file_enable = 1;
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// Wait a few cycles to observe
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#20;
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wait(done_writing_to_file);
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#20
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$finish;
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end
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endmodule
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