104 lines
2.2 KiB
Verilog
104 lines
2.2 KiB
Verilog
`timescale 1ns / 1ps
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module top_controller_module_tb;
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// Parameters
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parameter DATA_WIDTH = 16;
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parameter MEM_ROWS = 20;//20
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parameter MEM_COLS = 100;//80
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parameter OUTPUT_COL = 20;
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parameter OUTPUT_ROW = 20;
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parameter COMMON_ROW_COL = 4;
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parameter PE_ROWS = 20;
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parameter PE_COLS = 20;
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parameter H_LIMIT = 2;//header count
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parameter TOP_K = 4;
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// Inputs
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reg clk;
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reg rst;
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reg enable_top;
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reg write_back_to_file_enable_top;
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// Outputs
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wire done_top;
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wire done_writing_to_file_top;
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integer cycle_count;
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// Instantiate the DUT (Device Under Test)
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top_controller_module #(
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.DATA_WIDTH(DATA_WIDTH),
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.MEM_ROWS(MEM_ROWS),
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.MEM_COLS(MEM_COLS),
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.OUTPUT_COL(OUTPUT_COL),
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.OUTPUT_ROW(OUTPUT_ROW),
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.COMMON_ROW_COL(COMMON_ROW_COL),
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.PE_ROWS(PE_ROWS),
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.PE_COLS(PE_COLS),
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.H_LIMIT(H_LIMIT),
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.TOP_K(TOP_K)
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) uut (
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.clk(clk),
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.rst(rst),
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.enable_top(enable_top),
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.write_back_to_file_enable_top(write_back_to_file_enable_top),
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.done_top(done_top),
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.done_writing_to_file_top(done_writing_to_file_top)
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);
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// Cycle counting
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always @(posedge clk) begin
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if (rst) begin
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cycle_count <= 0;
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end else if (enable_top && !done_top) begin
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cycle_count <= cycle_count + 1;
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end
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end
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// Clock Generation: 10ns period (100MHz)
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initial begin
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clk = 0;
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forever #5 clk = ~clk;
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end
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// Test Stimulus
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initial begin
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// Initialize signals
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cycle_count <= 0;
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rst = 1;
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enable_top = 0;
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write_back_to_file_enable_top = 0;
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// Hold reset for a few cycles
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#20;
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rst = 0;
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// Enable top controller
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#30;
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enable_top = 1;
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write_back_to_file_enable_top = 0;
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wait(done_top);
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$display("Top controller Operation completed in %0d cycles", cycle_count);
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#50;
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write_back_to_file_enable_top = 1;
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wait(done_writing_to_file_top);
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// Stop simulation
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$display("Simulation finished.");
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$stop;
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end
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// // Monitor output states
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// initial begin
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// $monitor("Time=%t | enable_top=%b | done_top=%b | done_writing_to_file_top=%b",
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// $time, enable_top, done_top, done_writing_to_file_top);
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// end
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endmodule
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