DMA_for_RoCC/DMA_CONTROLLER.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

----------------------DMA Controller Entity---------------------------
entity DMA_Controller is
    port(
        clk                           : in  std_logic; 
        rst                           : in  std_logic;       
        rx_packet_length_noc_to_DMA   : in  std_logic_vector(4 downto 0);  --To DMA From Noc
        Receive_valid_to_DMA_from_Noc : in  std_logic;                     --To DMA From Noc 
        Sent_Ack_to_DMA_from_Noc      : in  std_logic_vector(4 downto 0);--------To DMA From Noc
        Funct_core_to_DMA             : in  std_logic_vector(6 downto 0);  --To DMA From Core 
        Address_core_to_DMA           : in  std_logic_vector(6 downto 0);  --To DMA From Core 
        Size_core_to_DMA              : in  std_logic_vector(4 downto 0);  --To DMA From Core
        Address_bus_From_DMA          : out std_logic_vector(7 downto 0);  --From DMA To RAM
        Read_write_Enable_From_DMA    : out std_logic_vector(1 downto 0);  --From DMA To RAM
        Sent_valid_from_DMA_to_NoC    : out std_logic;                     --From DMA To NoC     
        tx_packet_length_noc_From_DMA : out std_logic_vector(4 downto 0);  --From DMA To NoC
        Data_trans_from_DMA_to_core   : out std_logic_vector(4 downto 0)   --From DMA To Core
        );
end entity;

----------------------DMA Controller Behaviour------------------------

architecture DMA_Controller_Arch of DMA_Controller is
    Signal Count_from_NoC            : std_logic_vector(4 downto 0);
    Signal Count_to_NoC              : std_logic_vector(4 downto 0);
    Signal Address_to_RAM            : std_logic_vector(6 downto 0);


begin
    process(clk, rst)
    begin
        if rst = '0' then
            Sent_valid_from_DMA_to_NoC    <= '0';
            Address_bus_From_DMA          <= (others => '0');        
            Read_write_Enable_From_DMA    <= (others => '0');       
            tx_packet_length_noc_From_DMA <= (others => '0');
            Data_trans_from_DMA_to_core   <= (others => '0');
            Count_from_NoC                <= (others => '0');
            Count_to_NoC                  <= (others => '0');
            Address_to_RAM                <= (others => '0');

           
        elsif rising_edge(clk) then
----------------------Writing to RAM from NOC------------------------

            if Funct_core_to_DMA = "111 1111" then --- x"7f" is just randomly choosen value <[need to find an funct]> 
                if Count_from_NoC < Size_core_to_DMA then --comparing rx_packet_length_noc_to_DMA = Size_core_to_DMA 
                    if Count_from_NoC  = "00000" then
                        Address_to_RAM         <= Address_core_to_DMA;
                    end if;
                    if Receive_valid_to_DMA_from_Noc = '1' then
                        Address_bus_From_DMA        <= Address_to_RAM;
                        Read_write_Enable_From_DMA  <= "01";             --Write Enable
                        Data_trans_from_DMA_to_core <= Count_from_NoC;
                        Address_to_RAM              <= Address_to_RAM + 1;
                        Count_from_NoC              <= Count_from_NoC   + 1;

                    end if;
                end if;
            else
                Count_from_NoC                     <= (others => '0');
                Read_write_Enable_From_DMA         <= (others => '0');       

            end if;

----------------------Reading from RAM to NOC------------------------
            if Funct_core_to_DMA = "111 0000" then --- x"70" is just randomly choosen value <[need to find an funct]> 
                if Count_to_NoC < Size_core_to_DMA then --Sent_Ack_to_DMA_from_Noc could be used instead of the count to Noc
                    if Count_to_NoC  = "00000" then
                        Address_to_RAM                <= Address_core_to_DMA;
                        tx_packet_length_noc_From_DMA <= Size_core_to_DMA; --giving the size to the header of the NoC flit
                    end if;
                    Address_bus_From_DMA        <= Address_to_RAM;
                    Read_write_Enable_From_DMA  <= "10";             --Write Enable
                    Data_trans_from_DMA_to_core <= Sent_Ack_to_DMA_from_Noc;
                    Address_to_RAM              <= Address_to_RAM + 1;
                    Count_to_NoC                <= Count_to_NoC   + 1;
                    Sent_valid_from_DMA_to_NoC  <= '1';

                end if;
            else
                Count_from_NoC                  <= (others => '0');
                Read_write_Enable_From_DMA      <= (others => '0');       

            end if;
        end if;
    end process;
end architecture;