kkoloth
91dbf4503c
Implementation of the DMA logic up to 2/12/24. [Note: Testbench creation and full_DMA signal mapping is pending]
92 lines
4.7 KiB
VHDL
92 lines
4.7 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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----------------------DMA Controller Entity---------------------------
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entity DMA_Controller is
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port(
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clk : in std_logic;
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rst : in std_logic;
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rx_packet_length_noc_to_DMA : in std_logic_vector(4 downto 0); --To DMA From Noc
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Receive_valid_to_DMA_from_Noc : in std_logic; --To DMA From Noc
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Sent_Ack_to_DMA_from_Noc : in std_logic_vector(4 downto 0);--------To DMA From Noc
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Funct_core_to_DMA : in std_logic_vector(6 downto 0); --To DMA From Core
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Address_core_to_DMA : in std_logic_vector(6 downto 0); --To DMA From Core
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Size_core_to_DMA : in std_logic_vector(4 downto 0); --To DMA From Core
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Address_bus_From_DMA : out std_logic_vector(7 downto 0); --From DMA To RAM
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Read_write_Enable_From_DMA : out std_logic_vector(1 downto 0); --From DMA To RAM
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Sent_valid_from_DMA_to_NoC : out std_logic; --From DMA To NoC
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tx_packet_length_noc_From_DMA : out std_logic_vector(4 downto 0); --From DMA To NoC
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Data_trans_from_DMA_to_core : out std_logic_vector(4 downto 0) --From DMA To Core
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);
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end entity;
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----------------------DMA Controller Behaviour------------------------
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architecture DMA_Controller_Arch of DMA_Controller is
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Signal Count_from_NoC : std_logic_vector(4 downto 0);
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Signal Count_to_NoC : std_logic_vector(4 downto 0);
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Signal Address_to_RAM : std_logic_vector(6 downto 0);
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begin
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process(clk, rst)
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begin
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if rst = '0' then
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Sent_valid_from_DMA_to_NoC <= '0';
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Address_bus_From_DMA <= (others => '0');
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Read_write_Enable_From_DMA <= (others => '0');
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tx_packet_length_noc_From_DMA <= (others => '0');
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Data_trans_from_DMA_to_core <= (others => '0');
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Count_from_NoC <= (others => '0');
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Count_to_NoC <= (others => '0');
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Address_to_RAM <= (others => '0');
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elsif rising_edge(clk) then
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----------------------Writing to RAM from NOC------------------------
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if Funct_core_to_DMA = "111 1111" then --- x"7f" is just randomly choosen value <[need to find an funct]>
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if Count_from_NoC < Size_core_to_DMA then --comparing rx_packet_length_noc_to_DMA = Size_core_to_DMA
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if Count_from_NoC = "00000" then
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Address_to_RAM <= Address_core_to_DMA;
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end if;
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if Receive_valid_to_DMA_from_Noc = '1' then
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Address_bus_From_DMA <= Address_to_RAM;
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Read_write_Enable_From_DMA <= "01"; --Write Enable
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Data_trans_from_DMA_to_core <= Count_from_NoC;
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Address_to_RAM <= Address_to_RAM + 1;
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Count_from_NoC <= Count_from_NoC + 1;
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end if;
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end if;
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else
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Count_from_NoC <= (others => '0');
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Read_write_Enable_From_DMA <= (others => '0');
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end if;
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----------------------Reading from RAM to NOC------------------------
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if Funct_core_to_DMA = "111 0000" then --- x"70" is just randomly choosen value <[need to find an funct]>
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if Count_to_NoC < Size_core_to_DMA then --Sent_Ack_to_DMA_from_Noc could be used instead of the count to Noc
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if Count_to_NoC = "00000" then
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Address_to_RAM <= Address_core_to_DMA;
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tx_packet_length_noc_From_DMA <= Size_core_to_DMA; --giving the size to the header of the NoC flit
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end if;
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Address_bus_From_DMA <= Address_to_RAM;
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Read_write_Enable_From_DMA <= "10"; --Write Enable
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Data_trans_from_DMA_to_core <= Sent_Ack_to_DMA_from_Noc;
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Address_to_RAM <= Address_to_RAM + 1;
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Count_to_NoC <= Count_to_NoC + 1;
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Sent_valid_from_DMA_to_NoC <= '1';
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end if;
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else
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Count_from_NoC <= (others => '0');
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Read_write_Enable_From_DMA <= (others => '0');
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end if;
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end if;
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end process;
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end architecture;
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