DMA_for_RoCC/DMA_CONTROLLER.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

----------------------DMA Controller Entity---------------------------
entity DMA_Controller is
    -- constant DATA_SIZE    : integer := 7; -- Define constant for vector size for data of 8 bits
    -- constant ADDRESS_SIZE : integer := 6; -- Define constant for vector size for address 7 bits  
    -- constant ID_SIZE      : integer := 4; -- Define constant for vector size for size of Id's 5 bits  
    generic (
        DATA_SIZE    : integer := 7; -- Define constant for vector size for data of 8 bits
        ADDRESS_SIZE : integer := 6; -- Define constant for vector size for address 7 bits  
        ID_SIZE      : integer := 4 -- Define constant for vector size for size of Id's 5 bits  
    ); 
    port(
        clk                           : in  std_logic; 
        rst                           : in  std_logic;       
        rx_packet_length_noc_to_DMA   : in  std_logic_vector(ID_SIZE      downto 0);  --To DMA From Noc
        Receive_valid_to_DMA_from_Noc : in  std_logic;                                --To DMA From Noc 
        Sent_Ack_to_DMA_from_Noc      : in  std_logic_vector(ID_SIZE      downto 0);--------To DMA From Noc
        Funct_core_to_DMA             : in  std_logic_vector(ADDRESS_SIZE downto 0);  --To DMA From Core 
        Address_core_to_DMA           : in  std_logic_vector(ADDRESS_SIZE downto 0);  --To DMA From Core 
        Size_core_to_DMA              : in  std_logic_vector(ID_SIZE      downto 0);  --To DMA From Core
        Address_bus_From_DMA          : out std_logic_vector(ADDRESS_SIZE    downto 0);  --From DMA To RAM
        Read_Enable_From_DMA          : out std_logic;                                --From DMA To RAM
        Write_Enable_From_DMA         : out std_logic;                                --From DMA To RAM
        Sent_valid_from_DMA_to_NoC    : out std_logic;                                --From DMA To NoC     
        tx_packet_length_noc_From_DMA : out std_logic_vector(ID_SIZE      downto 0);  --From DMA To NoC
        Data_trans_from_DMA_to_core   : out std_logic_vector(ID_SIZE      downto 0)   --From DMA To Core
        );
end entity;

----------------------DMA Controller Behaviour------------------------

architecture DMA_Controller_Arch of DMA_Controller is
    Signal Count_from_NoC            : std_logic_vector(ID_SIZE downto 0);
    Signal Count_to_NoC              : std_logic_vector(ID_SIZE downto 0);
    Signal Address_to_RAM            : std_logic_vector(ADDRESS_SIZE downto 0);


begin
    process(clk, rst)
    begin
        if rst = '0' then
            Sent_valid_from_DMA_to_NoC    <= '0';
            Read_Enable_From_DMA          <= '0';
            Write_Enable_From_DMA         <= '0';
            Address_bus_From_DMA          <= (others => '0');        
            tx_packet_length_noc_From_DMA <= (others => '0');
            Data_trans_from_DMA_to_core   <= (others => '0');
            Count_from_NoC                <= (others => '0');
            Count_to_NoC                  <= (others => '0');
            Address_to_RAM                <= (others => '0');

           
        elsif rising_edge(clk) then
----------------------Writing to RAM from NOC------------------------

            if Funct_core_to_DMA = std_logic_vector(to_unsigned(15, 7)) then             --- x"0f" 15 Its arbitarly choosen from RoCC_Interface 
                if unsigned(Count_to_NoC) < (unsigned(Size_core_to_DMA)) then --+10 will reproduce same valid signal comparing rx_packet_length_noc_to_DMA = Size_core_to_DMA 
                    if Count_to_NoC  = "00000" then ---count_from_Noc but not working in the wave simulation
                        Address_to_RAM         <= Address_core_to_DMA;
                        Count_to_NoC           <= std_logic_vector(unsigned(Count_to_NoC) + 1);
                        --Write_Enable_From_DMA       <= '1';             --Write Enable
                    --end if;
                    elsif Receive_valid_to_DMA_from_Noc = '1' then
                        Address_bus_From_DMA        <= Address_to_RAM;
                        --report "Write_Enable_From_DMA is 1 from Line 68";
                        Write_Enable_From_DMA       <= '1';             --Write Enable ----<<<<Why the value is not updateded>>>>
                        Read_Enable_From_DMA        <= '0'; --'0'
                        Data_trans_from_DMA_to_core <= Count_to_NoC ;--  std_logic_vector(unsigned(Count_to_NoC) - 1)
                        Address_to_RAM              <= std_logic_vector(unsigned(Address_to_RAM) + 1);
                        Count_to_NoC                <= std_logic_vector(unsigned(Count_to_NoC) + 1);
                    else 
                        ----report "Write_Enable_From_DMA is 0 from Line 75";
                        Write_Enable_From_DMA       <= '0';             --Write Enable ----<<<<Why the value is not updateded>>>>
                        Read_Enable_From_DMA        <= '0'; --'0'
                    end if;
            
                else 
                    ----report "Write_Enable_From_DMA is 0 from Line 75";
                    Write_Enable_From_DMA       <= '0';             --Write Enable ----<<<<Why the value is not updateded>>>>
                    Read_Enable_From_DMA        <= '0'; --'0'
                end if;
            -- else
            --     Count_from_NoC                     <= (others => '0');
            --     Read_Enable_From_DMA               <= '0';
            --     Write_Enable_From_DMA              <= 'Z';--'0';     
            --     Sent_valid_from_DMA_to_NoC         <= '0';
            -- end if;

----------------------Reading from RAM to NOC------------------------
            elsif Funct_core_to_DMA = std_logic_vector(to_unsigned(127, 7)) then           ---  x"7f" 127 Its arbitarly choosen from RoCC_Interface  
                if unsigned(Count_to_NoC) < unsigned(Size_core_to_DMA) then --Sent_Ack_to_DMA_from_Noc could be used instead of the count to Noc
                    if Count_to_NoC  = "00000" then
                        Address_to_RAM                <= Address_core_to_DMA;
                        tx_packet_length_noc_From_DMA <= Size_core_to_DMA; --giving the size to the header of the NoC flit
                        Count_to_NoC                <= std_logic_vector(unsigned(Count_to_NoC) + 1);
                        ---Sent_valid_from_DMA_to_NoC  <= '1';
                    else
                        Address_bus_From_DMA        <= Address_to_RAM;
                        Write_Enable_From_DMA       <= '0';             
                        Read_Enable_From_DMA        <= '1';              --Read Enable
                        Data_trans_from_DMA_to_core <= Sent_Ack_to_DMA_from_Noc;
                        Address_to_RAM              <= std_logic_vector(unsigned(Address_to_RAM) + 1);
                        Count_to_NoC                <= std_logic_vector(unsigned(Count_to_NoC) + 1);
                        Sent_valid_from_DMA_to_NoC  <= '1';
                    end if;
                elsif unsigned(Count_to_NoC) < (unsigned(Size_core_to_DMA)+2) then
                    Count_to_NoC                <= std_logic_vector(unsigned(Count_to_NoC) + 1);
                    Sent_valid_from_DMA_to_NoC  <= '1';
                else
                    Read_Enable_From_DMA                <= '0';
                    Write_Enable_From_DMA               <= '0';
                    Sent_valid_from_DMA_to_NoC          <= '0';      
                end if;
            else
                Count_to_NoC                        <= (others => '0');
                Read_Enable_From_DMA                <= '0';
                --report "Write_Enable_From_DMA is 0 from Line 111";
                Write_Enable_From_DMA               <= '0';
                Sent_valid_from_DMA_to_NoC          <= '0';      
            end if;
        end if;
    end process;
end architecture;