171 lines
8.5 KiB
VHDL
171 lines
8.5 KiB
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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---vsim -gui work.fulldmatb
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entity fulldmaTB is
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end entity;
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architecture fulldmaTB_arch of fulldmaTB is
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constant DATA_SIZE : integer := 7; -- Define constant for vector size for data of 8 bits
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constant INST_SIZE : integer := 6; -- Define constant for vector size for inst of 6 bits
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constant LENGTH : integer := 4; -- Define constant for vector size for size of Id's 5 bits
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constant PACKET : integer := 31; -- Define constant for vector size for size of packet 32 bits
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constant REG_SIZE : integer := 63; -- Define constant for vector size for size of Reg 64 bits
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component Full_DMA is
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generic (
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DATA_SIZE : integer := 7; -- Define constant for vector size for data of 8 bits
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INST_SIZE : integer := 6; -- Define constant for vector size for inst of 6 bits
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LENGTH : integer := 4; -- Define constant for vector size for size of Id's 5 bits
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PACKET : integer := 31; -- Define constant for vector size for size of packet 32 bits
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REG_SIZE : integer := 63; -- Define constant for vector size for size of Reg 64 bits
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SOURCE_ID_NEW : std_logic_vector(5 downto 0) := "000000"; -- Default source ID should be changed
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DEST_ID_NEW : std_logic_vector(5 downto 0) := "000001" -- Default destination ID should be changed
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);
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port(
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clk : in std_logic;
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rst : in std_logic;
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local_noc_rx : in std_logic_vector(PACKET downto 0);--- --From Noc
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local_vc_write_tx_noc : in std_logic; ---_vector(192-1 downto 0);--From NoC
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cmd_valid : in std_logic; --From Core
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Cmd_inst_funct : in std_logic_vector(INST_SIZE downto 0); --From Core
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Cmd_inst_opcode : in std_logic_vector(INST_SIZE downto 0); --From Core
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Cmd_inst_rd : in std_logic_vector(LENGTH downto 0); --From Core
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Cmd_inst_rs1 : in std_logic_vector(LENGTH downto 0); --From Core
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Cmd_inst_rs2 : in std_logic_vector(LENGTH downto 0); --From Core
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Cmd_inst_xd : in std_logic; --From Core
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Cmd_inst_xs1 : in std_logic; --From Core
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Cmd_inst_xs2 : in std_logic; --From Core
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Cmd_rs1 : in std_logic_vector(REG_SIZE downto 0); --From Core
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Cmd_rs2 : in std_logic_vector(REG_SIZE downto 0); --From Core
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Cmd_busy : out std_logic; --To Core
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Cmd_ready : out std_logic; --To Core --always one
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local_noc_tx : out std_logic_vector(PACKET downto 0);--- --To NoC
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local_vc_write_rx_noc : out std_logic ---_vector(192-1 downto 0); --To NoC
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);
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end component;
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signal clk_tb : std_logic;
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signal rst_tb : std_logic;
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signal local_noc_rx1, local_noc_rx2 : std_logic_vector(PACKET downto 0);
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signal local_vc_write_tx_noc1 : std_logic;
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signal cmd_valid,local_vc_write_tx_noc2 : std_logic;
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signal Cmd_inst_funct1,Cmd_inst_funct2 : std_logic_vector(INST_SIZE downto 0);
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signal Cmd_inst_opcode : std_logic_vector(INST_SIZE downto 0);
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signal Cmd_inst_rd : std_logic_vector(LENGTH downto 0);
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signal Cmd_inst_rs1 : std_logic_vector(LENGTH downto 0);
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signal Cmd_inst_rs2 : std_logic_vector(LENGTH downto 0);
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signal Cmd_inst_xd : std_logic;
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signal Cmd_inst_xs1 : std_logic;
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signal Cmd_inst_xs2 : std_logic;
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signal Cmd_rs1_1, Cmd_rs1_2 : std_logic_vector(REG_SIZE downto 0);
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signal Cmd_rs2_1, Cmd_rs2_2 : std_logic_vector(REG_SIZE downto 0);
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signal Cmd_busy : std_logic;
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signal Cmd_ready : std_logic;
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signal local_noc_tx1, local_noc_tx2 : std_logic_vector(PACKET downto 0);
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signal local_vc_write_rx_noc : std_logic;
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begin
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-- Component instantiation with a label
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fulldma_inst1 : Full_DMA
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generic map (
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SOURCE_ID_NEW => "000001", -- Set source ID
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DEST_ID_NEW => "000000" -- Set destination ID
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)
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port map (
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clk => clk_tb,
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rst => rst_tb,
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local_noc_rx => local_noc_rx1,
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local_vc_write_tx_noc => local_vc_write_tx_noc1,
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cmd_valid => cmd_valid,
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Cmd_inst_funct => Cmd_inst_funct1,
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Cmd_inst_opcode => Cmd_inst_opcode,
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Cmd_inst_rd => Cmd_inst_rd,
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Cmd_inst_rs1 => Cmd_inst_rs1,
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Cmd_inst_rs2 => Cmd_inst_rs2,
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Cmd_inst_xd => Cmd_inst_xd,
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Cmd_inst_xs1 => Cmd_inst_xs1,
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Cmd_inst_xs2 => Cmd_inst_xs2,
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Cmd_rs1 => Cmd_rs1_1,
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Cmd_rs2 => Cmd_rs2_1,
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Cmd_busy => Cmd_busy,
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Cmd_ready => Cmd_ready,
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local_noc_tx => local_noc_tx1,
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local_vc_write_rx_noc => local_vc_write_rx_noc
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);
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-- Component instantiation with a label
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fulldma_inst2 : Full_DMA
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generic map (
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SOURCE_ID_NEW => "000000", -- Set source ID
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DEST_ID_NEW => "000001" -- Set destination ID
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)
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port map (
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clk => clk_tb,
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rst => rst_tb,
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local_noc_rx => local_noc_rx2,
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local_vc_write_tx_noc => local_vc_write_tx_noc2,
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cmd_valid => cmd_valid,
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Cmd_inst_funct => Cmd_inst_funct2,
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Cmd_inst_opcode => Cmd_inst_opcode,
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Cmd_inst_rd => Cmd_inst_rd,
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Cmd_inst_rs1 => Cmd_inst_rs1,
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Cmd_inst_rs2 => Cmd_inst_rs2,
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Cmd_inst_xd => Cmd_inst_xd,
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Cmd_inst_xs1 => Cmd_inst_xs1,
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Cmd_inst_xs2 => Cmd_inst_xs2,
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Cmd_rs1 => Cmd_rs1_2,
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Cmd_rs2 => Cmd_rs2_2,
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Cmd_busy => Cmd_busy,
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Cmd_ready => Cmd_ready,
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local_noc_tx => local_noc_tx2,
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local_vc_write_rx_noc => local_vc_write_rx_noc
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);
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-- Clock generation process
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clk_process: process
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begin
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clk_tb <= '0'; wait for 5 ns;
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clk_tb <= '1'; wait for 5 ns;
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end process;
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-----------------------NoC connection has to be changed--------------------
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local_noc_rx1 <= local_noc_tx2;
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local_noc_rx2 <= local_noc_tx1;
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-- Simulation process to assign values to CtrlCommand
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simproc: process
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begin
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local_vc_write_tx_noc2 <= '0';
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cmd_valid <= '0';
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rst_tb <= '0';
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wait for 10 ns;
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rst_tb <= '1';
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wait for 40 ns;
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Cmd_inst_funct2 <= "0011110"; --#define DMA_WRITE_TO_RAM 30 /// 0X1E
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Cmd_inst_funct1 <= "0011111"; --#define DMA_READ_FROM_RAM 31 /// 0X1F
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Cmd_rs1_1 <= std_logic_vector(to_unsigned(0, 57)) & "0000010"; --7 bit address & 57 bit zeros
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Cmd_rs1_2 <= std_logic_vector(to_unsigned(0, 57)) & "0001000"; --7 bit address & 57 bit zeros
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Cmd_rs2_1 <= std_logic_vector(to_unsigned(0, 59)) & "00100"; --5 bit size & 59 bit zeros
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Cmd_rs2_2 <= std_logic_vector(to_unsigned(0, 59)) & "00100"; --5 bit size & 59 bit zeros
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wait for 20 ns;
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cmd_valid <= '1';
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wait for 40 ns;
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cmd_valid <= '0';
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local_vc_write_tx_noc2 <= '1';
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wait for 80 ns;
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local_vc_write_tx_noc2 <= '0';
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wait for 1000 ns;
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-- wait for 1000 ns ;
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end process;
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end architecture;
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