DMA_for_RoCC/FULL_DMA.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

----------------------Full DMA Entity---------------------------
entity full_dma is
    -- constant DATA_SIZE        : integer := 7; -- Define constant for vector size for data of 8 bits
    -- constant INST_SIZE        : integer := 6;  -- Define constant for vector size for inst of 6 bits
    -- constant LENGTH           : integer := 4;  -- Define constant for vector size for size of Id's 5 bits
    -- constant PACKET           : integer := 31; -- Define constant for vector size for size of packet 32 bits
    -- constant REG_SIZE         : integer := 63; -- Define constant for vector size for size of Reg 64 bits    
    generic (
        DATA_SIZE             : natural := 7; -- Define constant for vector size for data of 8 bits
        INST_SIZE             : natural := 6;  -- Define constant for vector size for inst of 6 bits
        LENGTH                : natural := 4;  -- Define constant for vector size for size of Id's 5 bits
        PACKET                : natural := 31; -- Define constant for vector size for size of packet 32 bits
        REG_SIZE              : natural := 63; -- Define constant for vector size for size of Reg 64 bits 
        SOURCE_ID_NEW         : std_logic_vector(5 downto 0) := "000000"; -- Default source ID should be changed
        DEST_ID_NEW           : std_logic_vector(5 downto 0) := "000001"  -- Default destination ID should be changed
    );    
    port(
        clk                   : in  std_logic; 
        rst                   : in  std_logic;       
        local_noc_rx          : in  std_logic_vector(PACKET downto 0);--- --From Noc 
        local_vc_write_rx_noc : in  std_logic; ---_vector(192-1 downto 0);--From NoC
        local_incr_rx_vec_noc : in  std_logic;
        cmd_valid             : in  std_logic;                            --From Core
        cmd_inst_funct        : in  std_logic_vector(INST_SIZE downto 0); --From Core
        cmd_inst_opcode       : in  std_logic_vector(INST_SIZE downto 0); --From Core
        cmd_inst_rd           : in  std_logic_vector(LENGTH downto 0);    --From Core
        cmd_inst_rs1          : in  std_logic_vector(LENGTH downto 0);    --From Core
        cmd_inst_rs2          : in  std_logic_vector(LENGTH downto 0);    --From Core
        cmd_inst_xd           : in  std_logic;                            --From Core
        cmd_inst_xs1          : in  std_logic;                            --From Core
        cmd_inst_xs2          : in  std_logic;                            --From Core
        cmd_rs1               : in  std_logic_vector(REG_SIZE downto 0);  --From Core
        cmd_rs2               : in  std_logic_vector(REG_SIZE downto 0);  --From Core
        cmd_busy              : out std_logic;                            --To Core 
        cmd_ready             : out std_logic;                            --To Core --always one
        local_noc_tx          : out std_logic_vector(PACKET downto 0);--- --To NoC
        local_vc_write_tx_noc : out std_logic; ---_vector(192-1 downto 0);--To NoC
        local_incr_tx_vec_noc : out std_logic                             --To NoC      
        );
end entity;

----------------------Full DMA Behaviour------------------------

architecture full_dma_arch of full_dma is
    component single_port_ram is
        port(
            clk               : in  std_logic; 
            rst               : in  std_logic;
            address_bus       : in  std_logic_vector(INST_SIZE downto 0); --From DMA
            read_enable       : in  std_logic; --From DMA
            write_enable      : in  std_logic; --From DMA
            data_bus_in       : in  std_logic_vector(DATA_SIZE downto 0); --From Noc
            data_bus_out      : out std_logic_vector(DATA_SIZE downto 0)  --From Noc
            );
    end component;
    component noc_interface is
        generic (
            SOURCE_ID            : std_logic_vector(5 downto 0) := "000000";    -- Default source ID should be changed
            DEST_ID              : std_logic_vector(5 downto 0) := "000001"     -- Default destination ID should be changed
        );
        port(
            clk                  : in  std_logic; 
            rst                  : in  std_logic;
            sent_valid_from_dma  : in  std_logic;                                  --From DMA
            data_bus_noc_in      : in  std_logic_vector(DATA_SIZE downto 0);       --From RAM
            tx_packet_length_noc : in  std_logic_vector(LENGTH downto 0);          --From DMA
            local_noc_rx         : in  std_logic_vector(REG_SIZE downto 0);---     --From Noc 
            local_vc_write_rx_noc: in  std_logic; ---_vector(192-1 downto 0);      --From NoC
            local_incr_rx_vec_noc: in  std_logic;                                  --From NoC
            rx_packet_length_noc : out std_logic_vector(LENGTH downto 0);          --To DMA
            local_noc_tx         : out std_logic_vector(REG_SIZE downto 0);---     --To NoC
            local_vc_write_tx_noc: out std_logic; ---_vector(192-1 downto 0);      --To NoC
            local_incr_tx_vec_noc: out std_logic;                                  --To NoC
            receive_valid_to_dma : out std_logic;                                  --To DMA 
            sent_ack_to_dma      : out std_logic_vector(LENGTH downto 0);--------- --To DMA
            data_bus_noc_out         : out std_logic_vector(DATA_SIZE downto 0)        --To RAM
            );
    end component;
    component rocc_interface is
        port(
            clk                  : in  std_logic; 
            rst                  : in  std_logic;       
            cmd_valid            : in  std_logic;                                --From Core
            cmd_inst_funct       : in  std_logic_vector(INST_SIZE downto 0);     --From Core
            cmd_inst_opcode      : in  std_logic_vector(INST_SIZE downto 0);     --From Core
            cmd_inst_rd          : in  std_logic_vector(LENGTH downto 0);        --From Core
            cmd_inst_rs1         : in  std_logic_vector(LENGTH downto 0);        --From Core
            cmd_inst_rs2         : in  std_logic_vector(LENGTH downto 0);        --From Core
            cmd_inst_xd          : in  std_logic;                                --From Core
            cmd_inst_xs1         : in  std_logic;                                --From Core
            cmd_inst_xs2         : in  std_logic;                                --From Core
            cmd_rs1              : in  std_logic_vector(REG_SIZE downto 0);      --From Core
            cmd_rs2              : in  std_logic_vector(REG_SIZE downto 0);      --From Core
            data_trans_from_dma  : in  std_logic_vector(LENGTH downto 0);        --From DMA
            cmd_busy             : out std_logic;                                --To Core 
            cmd_ready            : out std_logic;                                --To Core --always one
            funct_to_dma         : out std_logic_vector(INST_SIZE downto 0);     --To DMA  
            address_to_dma       : out std_logic_vector(INST_SIZE downto 0);     --To DMA  
            size_to_dma          : out std_logic_vector(LENGTH downto 0)         --To DMA  
            );
    end component;
    component dma_controller is
        port(
            clk                           : in  std_logic; 
            rst                           : in  std_logic;       
            rx_packet_length_noc_to_dma   : in  std_logic_vector(LENGTH downto 0);      --To DMA From Noc
            receive_valid_to_dma_from_noc : in  std_logic;                              --To DMA From Noc 
            sent_ack_to_dma_from_noc      : in  std_logic_vector(LENGTH downto 0);--------To DMA From Noc
            funct_core_to_dma             : in  std_logic_vector(INST_SIZE downto 0);   --To DMA From Core 
            address_core_to_dma           : in  std_logic_vector(INST_SIZE downto 0);   --To DMA From Core 
            size_core_to_dma              : in  std_logic_vector(LENGTH downto 0);      --To DMA From Core
            address_bus_from_dma          : out std_logic_vector(INST_SIZE downto 0);   --From DMA To RAM
            read_enable_From_DMA          : out std_logic;                              --From DMA To RAM
            write_enable_from_dma         : out std_logic;                              --From DMA To RAM
            sent_valid_from_dma_to_noc    : out std_logic;                              --From DMA To NoC     
            tx_packet_length_noc_from_dma : out std_logic_vector(LENGTH downto 0);      --From DMA To NoC
            data_trans_from_dma_to_core   : out std_logic_vector(LENGTH downto 0)       --From DMA To Core
            );
    end component;

    
    signal address_bus_sig                   : std_logic_vector(INST_SIZE downto 0);
    signal read_enable_sig                   : std_logic; 
    signal write_enable_sig                  : std_logic; 
    --  signal Read_write_enable_sig             : std_logic_vector(1 downto 0);
    signal data_bus_in_sig                   : std_logic_vector(DATA_SIZE downto 0);
    signal data_bus_out_sig                  : std_logic_vector(DATA_SIZE downto 0);


    signal sent_valid_from_dma_sig           : std_logic;
    --signal data_bus_noc_in_sig               : std_logic_vector(DATA_SIZE downto 0);
    signal tx_packet_length_noc_sig          : std_logic_vector(LENGTH downto 0);
    signal rx_packet_length_noc_sig          : std_logic_vector(LENGTH downto 0);
    --signal local_noc_tx_sig                  : std_logic_vector(PACKET downto 0);
    --signal local_vc_write_rx_noc_sig         : std_logic;
    signal receive_valid_to_dma_sig          : std_logic;
    signal sent_ack_to_dma_sig               : std_logic_vector(LENGTH downto 0);
    --signal data_bus_noc_out    _sig              : std_logic_vector(DATA_SIZE downto 0);

    signal data_trans_from_dma_sig           : std_logic_vector(LENGTH downto 0);
    signal funct_to_dma_sig                  : std_logic_vector(INST_SIZE downto 0);
    signal address_to_dma_sig                : std_logic_vector(INST_SIZE downto 0);
    signal size_to_dma_sig                   : std_logic_vector(LENGTH downto 0);



    

    --signal rx_packet_length_noc_to_dma_sig   : std_logic_vector(LENGTH downto 0); 
   -- signal receive_valid_to_dma_from_noc_sig : std_logic;                    
    --signal sent_ack_to_dma_from_noc_sig      : std_logic_vector(LENGTH downto 0);
    --signal funct_core_to_dma_sig             : std_logic_vector(INST_SIZE downto 0); 
    --signal address_core_to_dma_sig           : std_logic_vector(INST_SIZE downto 0);  
    --Signal size_core_to_dma_sig              : std_logic_vector(LENGTH downto 0);  
    --signal address_bus_from_dma_sig          : std_logic_vector(DATA_SIZE downto 0); 
   -- signal Read_write_enable_from_dma_sig    : std_logic_vector(1 downto 0); 
    --signal sent_valid_from_dma_to_noc_sig    : std_logic;                     
    --signal tx_packet_length_noc_from_dma_sig : std_logic_vector(LENGTH downto 0); 
    --signal data_trans_from_dma_to_core_sig   : std_logic_vector(LENGTH downto 0);  





    begin 
    -- Single_Port_RAM mapping
    single_port_ram_inst : single_port_ram
    port map(
        clk               => clk,
        rst               => rst,
        address_bus       => address_bus_sig,
        read_enable       => read_enable_sig,
        write_enable      => write_enable_sig,
        data_bus_in       => data_bus_in_sig, -- Assuming data input comes from NoC
        data_bus_out      => data_bus_out_sig
    );


    -- Noc_Interface mapping
    noc_interface_inst : noc_interface
    generic map (
        SOURCE_ID => SOURCE_ID_NEW,
        DEST_ID   => DEST_ID_NEW
    )
    port map(
        clk                  => clk,
        rst                  => rst,
        sent_valid_from_dma  => sent_valid_from_dma_sig,
        data_bus_noc_in      => data_bus_out_sig,
        tx_packet_length_noc => tx_packet_length_noc_sig,
        local_noc_rx         => local_noc_rx,                 ---
        local_vc_write_rx_noc=> local_vc_write_rx_noc,        ---
        local_incr_rx_vec_noc=>local_incr_rx_vec_noc,         ---
        rx_packet_length_noc => rx_packet_length_noc_sig,
        local_noc_tx         => local_noc_tx,                 ---
        local_vc_write_tx_noc=> local_vc_write_tx_noc,        ---
        local_incr_tx_vec_noc=> local_incr_tx_vec_noc,        ---
        receive_valid_to_dma => receive_valid_to_dma_sig,
        sent_ack_to_dma      => sent_ack_to_dma_sig,
        data_bus_noc_out     => data_bus_in_sig
    );

    -- RoCC_Interface mapping
    rocc_interface_inst : rocc_interface
    port map(
        clk                 => clk,
        rst                 => rst,
        cmd_valid           => cmd_valid,                     ---         
        cmd_inst_funct      => cmd_inst_funct,                ---
        cmd_inst_opcode     => cmd_inst_opcode,               ---
        cmd_inst_rd         => cmd_inst_rd,                   ---
        cmd_inst_rs1        => cmd_inst_rs1,                  ---
        cmd_inst_rs2        => cmd_inst_rs2,                  ---
        cmd_inst_xd         => cmd_inst_xd,                   ---
        cmd_inst_xs1        => cmd_inst_xs1,                  ---
        cmd_inst_xs2        => cmd_inst_xs2,                  ---
        cmd_rs1             => cmd_rs1,                       ---
        cmd_rs2             => cmd_rs2,                       ---
        data_trans_from_dma => data_trans_from_dma_sig,
        cmd_busy            => cmd_busy,                      ---
        cmd_ready           => cmd_ready,                     ---
        funct_to_dma        => funct_to_dma_sig,
        address_to_dma      => address_to_dma_sig,
        size_to_dma         => size_to_dma_sig
    );

        -- DMA_Controller mapping
    dma_controller_inst : dma_controller
    port map(
        clk                           => clk,
        rst                           => rst,
        rx_packet_length_noc_to_dma   => rx_packet_length_noc_sig,
        receive_valid_to_dma_from_noc => receive_valid_to_dma_sig,
        sent_ack_to_dma_from_noc      => sent_ack_to_dma_sig,
        funct_core_to_dma             => funct_to_dma_sig,
        address_core_to_dma           => address_to_dma_sig,
        size_core_to_dma              => size_to_dma_sig,
        address_bus_from_dma          => address_bus_sig,
        read_enable_From_DMA          => read_enable_sig,      
        write_enable_from_dma         => write_enable_sig,                                
        sent_valid_from_dma_to_noc    => sent_valid_from_dma_sig,
        tx_packet_length_noc_from_dma => tx_packet_length_noc_sig,
        data_trans_from_dma_to_core   => data_trans_from_dma_sig
    );


end architecture;

    ----mapping need to be done yet-------------



    --     signal address_bus_sig                   : std_logic_vector(DATA_SIZE downto 0);
--   --  signal Read_write_enable_sig             : std_logic_vector(1 downto 0);
--     signal data_bus_in_sig                   : std_logic_vector(DATA_SIZE downto 0);
--     signal data_bus_out_sig                  : std_logic_vector(DATA_SIZE downto 0);

--     signal sent_valid_from_dma_sig           : std_logic;
--     signal data_bus_noc_in_sig               : std_logic_vector(DATA_SIZE downto 0);
--     signal tx_packet_length_noc_sig          : std_logic_vector(LENGTH downto 0);
--     signal rx_packet_length_noc_sig          : std_logic_vector(LENGTH downto 0);
--     signal local_noc_tx_sig                  : std_logic_vector(PACKET downto 0);
--     signal local_vc_write_rx_noc_sig         : std_logic;
--     signal receive_valid_to_dma_sig          : std_logic;
--     signal sent_ack_to_dma_sig               : std_logic_vector(LENGTH downto 0);
--     signal data_bus_noc_out    _sig              : std_logic_vector(DATA_SIZE downto 0);

--     signal data_trans_from_dma_sig           : std_logic_vector(LENGTH downto 0);
--     signal funct_to_dma_sig                  : std_logic_vector(INST_SIZE downto 0);
--     signal address_to_dma_sig                : std_logic_vector(INST_SIZE downto 0);
--     signal size_to_dma_sig                   : std_logic_vector(LENGTH downto 0);

--     signal rx_packet_length_noc_to_dma_sig   : std_logic_vector(LENGTH downto 0); 
--     signal receive_valid_to_dma_from_noc_sig : std_logic;                    
--     signal sent_ack_to_dma_from_noc_sig      : std_logic_vector(LENGTH downto 0);
--     signal funct_core_to_dma_sig             : std_logic_vector(INST_SIZE downto 0); 
--     signal address_core_to_dma_sig           : std_logic_vector(INST_SIZE downto 0);  
--     Signal size_core_to_dma_sig              : std_logic_vector(LENGTH downto 0);  
--     signal address_bus_from_dma_sig          : std_logic_vector(DATA_SIZE downto 0); 
--    -- signal Read_write_enable_from_dma_sig    : std_logic_vector(1 downto 0); 
--     signal sent_valid_from_dma_to_noc_sig    : std_logic;                     
--     signal tx_packet_length_noc_from_dma_sig : std_logic_vector(LENGTH downto 0); 
--     signal data_trans_from_dma_to_core_sig   : std_logic_vector(LENGTH downto 0);