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final working full DMA module

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root 2024-12-23 14:03:57 +01:00
parent eceea6c381
commit 13ab5916b4
6 changed files with 149 additions and 204 deletions
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34
DMA_CONTROLLER.vhd
View file

@ -4,9 +4,6 @@ use ieee.numeric_std.all;
----------------------DMA Controller Entity---------------------------
entity dma_controller is
-- constant DATA_SIZE : integer := 7; -- Define constant for vector size for data of 8 bits
-- constant ADDRESS_SIZE : integer := 6; -- Define constant for vector size for address 7 bits
-- constant ID_SIZE : integer := 4; -- Define constant for vector size for size of Id's 5 bits
generic (
RAM_WRITE_CMD : natural := 15; -- Writing to ram command from rocc
RAM_READ_CMD : natural := 127; -- Reading from ram command from rocc
@ -35,11 +32,8 @@ end entity;
----------------------DMA Controller Behaviour------------------------
architecture dma_controller_arch of dma_controller is
--Signal count_from_noc : std_logic_vector(ID_SIZE downto 0);
Signal count_to_noc : std_logic_vector(ID_SIZE downto 0);
Signal address_to_ram : std_logic_vector(ADDRESS_SIZE downto 0);
begin
process(clk, rst)
begin
@ -50,60 +44,52 @@ begin
address_bus_from_dma <= (others => '0');
tx_packet_length_noc_from_dma <= (others => '0');
data_trans_from_dma_to_core <= (others => '0');
-- count_from_noc <= (others => '0');
count_to_noc <= (others => '0');
address_to_ram <= (others => '0');
elsif rising_edge(clk) then
----------------------Writing to RAM from NOC------------------------
if funct_core_to_dma = std_logic_vector(to_unsigned(RAM_WRITE_CMD, DATA_SIZE)) then --- x"0f" 15 Its arbitarly choosen from RoCC_Interface
if unsigned(count_to_noc) < (unsigned(size_core_to_dma)) then --+10 will reproduce same valid signal comparing rx_packet_length_noc_to_dma = size_core_to_dma
if unsigned(count_to_noc) < (unsigned(size_core_to_dma)) then
if count_to_noc = "00000" then ---count_from_noc but not working in the wave simulation
address_to_ram <= address_core_to_dma;
count_to_noc <= std_logic_vector(unsigned(count_to_noc) + 1);
--write_enable_from_dma <= '1'; --Write Enable
--end if;
elsif receive_valid_to_dma_from_noc = '1' then
address_bus_from_dma <= address_to_ram;
--report "write_enable_from_dma is 1 from Line 68";
write_enable_from_dma <= '1'; --Write Enable ----<<<<Why the value is not updateded>>>>
write_enable_from_dma <= '1'; --Write Enable
read_enable_from_dma <= '0'; --'0'
data_trans_from_dma_to_core <= count_to_noc ;-- std_logic_vector(unsigned(count_to_noc) - 1)
address_to_ram <= std_logic_vector(unsigned(address_to_ram) + 1);
count_to_noc <= std_logic_vector(unsigned(count_to_noc) + 1);
else
----report "write_enable_from_dma is 0 from Line 75";
write_enable_from_dma <= '0'; --Write Enable ----<<<<Why the value is not updateded>>>>
write_enable_from_dma <= '0'; --Write Enable
read_enable_from_dma <= '0'; --'0'
end if;
else
----report "write_enable_from_dma is 0 from Line 75";
write_enable_from_dma <= '0'; --Write Enable ----<<<<Why the value is not updateded>>>>
write_enable_from_dma <= '0'; --Write Enable
read_enable_from_dma <= '0'; --'0'
count_to_noc <= (others => '0');
data_trans_from_dma_to_core <= (others => '0');
end if;
-- else
-- count_from_noc <= (others => '0');
-- read_enable_from_dma <= '0';
-- write_enable_from_dma <= 'Z';--'0';
-- sent_valid_from_dma_to_noc <= '0';
-- end if;
----------------------Reading from RAM to NOC------------------------
elsif funct_core_to_dma = std_logic_vector(to_unsigned(RAM_READ_CMD, DATA_SIZE)) then --- x"7f" 127 Its arbitarly choosen from RoCC_Interface
if unsigned(count_to_noc) < unsigned(size_core_to_dma) then --sent_ack_to_dma_from_noc could be used instead of the count to Noc
if unsigned(count_to_noc) < unsigned(size_core_to_dma) then
if count_to_noc = "00000" then
address_to_ram <= address_core_to_dma;
tx_packet_length_noc_from_dma <= size_core_to_dma; --giving the size to the header of the NoC flit
count_to_noc <= std_logic_vector(unsigned(count_to_noc) + 1);
---sent_valid_from_dma_to_noc <= '1';
else
address_bus_from_dma <= address_to_ram;
write_enable_from_dma <= '0';
read_enable_from_dma <= '1'; --Read Enable
data_trans_from_dma_to_core <= sent_ack_to_dma_from_noc;
data_trans_from_dma_to_core <= count_to_noc;--sent_ack_to_dma_from_noc;
address_to_ram <= std_logic_vector(unsigned(address_to_ram) + 1);
count_to_noc <= std_logic_vector(unsigned(count_to_noc) + 1);
sent_valid_from_dma_to_noc <= '1';
@ -115,6 +101,7 @@ begin
read_enable_from_dma <= '0';
write_enable_from_dma <= '0';
sent_valid_from_dma_to_noc <= '0';
count_to_noc <= (others => '0');
end if;
else
count_to_noc <= (others => '0');
@ -122,6 +109,7 @@ begin
--report "write_enable_from_dma is 0 from Line 111";
write_enable_from_dma <= '0';
sent_valid_from_dma_to_noc <= '0';
data_trans_from_dma_to_core <= (others => '0');
end if;
end if;
end process;

84
FULL_DMA.vhd
View file

@ -2,13 +2,9 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
----------------------Full DMA Entity---------------------------
----------------------------------------Full DMA Entity-------------------------------------------
entity full_dma is
-- constant DATA_SIZE : integer := 7; -- Define constant for vector size for data of 8 bits
-- constant INST_SIZE : integer := 6; -- Define constant for vector size for inst of 6 bits
-- constant LENGTH : integer := 4; -- Define constant for vector size for size of Id's 5 bits
-- constant PACKET : integer := 31; -- Define constant for vector size for size of packet 32 bits
-- constant REG_SIZE : integer := 63; -- Define constant for vector size for size of Reg 64 bits
generic (
DATA_SIZE : natural := 7; -- Define constant for vector size for data of 8 bits
INST_SIZE : natural := 6; -- Define constant for vector size for inst of 6 bits
@ -22,7 +18,7 @@ entity full_dma is
clk : in std_logic;
rst : in std_logic;
local_noc_rx : in std_logic_vector(PACKET downto 0);--- --From Noc
local_vc_write_rx_noc : in std_logic; ---_vector(192-1 downto 0);--From NoC
local_vc_write_rx_noc : in std_logic; --From NoC
local_incr_rx_vec_noc : in std_logic;
cmd_valid : in std_logic; --From Core
cmd_inst_funct : in std_logic_vector(INST_SIZE downto 0); --From Core
@ -38,12 +34,12 @@ entity full_dma is
cmd_busy : out std_logic; --To Core
cmd_ready : out std_logic; --To Core --always one
local_noc_tx : out std_logic_vector(PACKET downto 0);--- --To NoC
local_vc_write_tx_noc : out std_logic; ---_vector(192-1 downto 0);--To NoC
local_vc_write_tx_noc : out std_logic; --To NoC
local_incr_tx_vec_noc : out std_logic --To NoC
);
end entity;
----------------------Full DMA Behaviour------------------------
----------------------------------------Full DMA Behaviour-------------------------------------------
architecture full_dma_arch of full_dma is
component single_port_ram is
@ -69,11 +65,11 @@ architecture full_dma_arch of full_dma is
data_bus_noc_in : in std_logic_vector(DATA_SIZE downto 0); --From RAM
tx_packet_length_noc : in std_logic_vector(LENGTH downto 0); --From DMA
local_noc_rx : in std_logic_vector(REG_SIZE downto 0);--- --From Noc
local_vc_write_rx_noc: in std_logic; ---_vector(192-1 downto 0); --From NoC
local_vc_write_rx_noc: in std_logic; --From NoC
local_incr_rx_vec_noc: in std_logic; --From NoC
rx_packet_length_noc : out std_logic_vector(LENGTH downto 0); --To DMA
local_noc_tx : out std_logic_vector(REG_SIZE downto 0);--- --To NoC
local_vc_write_tx_noc: out std_logic; ---_vector(192-1 downto 0); --To NoC
local_vc_write_tx_noc: out std_logic; --To NoC
local_incr_tx_vec_noc: out std_logic; --To NoC
receive_valid_to_dma : out std_logic; --To DMA
sent_ack_to_dma : out std_logic_vector(LENGTH downto 0);--------- --To DMA
@ -126,46 +122,18 @@ architecture full_dma_arch of full_dma is
signal address_bus_sig : std_logic_vector(INST_SIZE downto 0);
signal read_enable_sig : std_logic;
signal write_enable_sig : std_logic;
-- signal Read_write_enable_sig : std_logic_vector(1 downto 0);
signal data_bus_in_sig : std_logic_vector(DATA_SIZE downto 0);
signal data_bus_out_sig : std_logic_vector(DATA_SIZE downto 0);
signal sent_valid_from_dma_sig : std_logic;
--signal data_bus_noc_in_sig : std_logic_vector(DATA_SIZE downto 0);
signal tx_packet_length_noc_sig : std_logic_vector(LENGTH downto 0);
signal rx_packet_length_noc_sig : std_logic_vector(LENGTH downto 0);
--signal local_noc_tx_sig : std_logic_vector(PACKET downto 0);
--signal local_vc_write_rx_noc_sig : std_logic;
signal receive_valid_to_dma_sig : std_logic;
signal sent_ack_to_dma_sig : std_logic_vector(LENGTH downto 0);
--signal data_bus_noc_out _sig : std_logic_vector(DATA_SIZE downto 0);
signal data_trans_from_dma_sig : std_logic_vector(LENGTH downto 0);
signal funct_to_dma_sig : std_logic_vector(INST_SIZE downto 0);
signal address_to_dma_sig : std_logic_vector(INST_SIZE downto 0);
signal size_to_dma_sig : std_logic_vector(LENGTH downto 0);
--signal rx_packet_length_noc_to_dma_sig : std_logic_vector(LENGTH downto 0);
-- signal receive_valid_to_dma_from_noc_sig : std_logic;
--signal sent_ack_to_dma_from_noc_sig : std_logic_vector(LENGTH downto 0);
--signal funct_core_to_dma_sig : std_logic_vector(INST_SIZE downto 0);
--signal address_core_to_dma_sig : std_logic_vector(INST_SIZE downto 0);
--Signal size_core_to_dma_sig : std_logic_vector(LENGTH downto 0);
--signal address_bus_from_dma_sig : std_logic_vector(DATA_SIZE downto 0);
-- signal Read_write_enable_from_dma_sig : std_logic_vector(1 downto 0);
--signal sent_valid_from_dma_to_noc_sig : std_logic;
--signal tx_packet_length_noc_from_dma_sig : std_logic_vector(LENGTH downto 0);
--signal data_trans_from_dma_to_core_sig : std_logic_vector(LENGTH downto 0);
begin
-- Single_Port_RAM mapping
single_port_ram_inst : single_port_ram
@ -179,7 +147,6 @@ architecture full_dma_arch of full_dma is
data_bus_out => data_bus_out_sig
);
-- Noc_Interface mapping
noc_interface_inst : noc_interface
generic map (
@ -246,43 +213,6 @@ architecture full_dma_arch of full_dma is
tx_packet_length_noc_from_dma => tx_packet_length_noc_sig,
data_trans_from_dma_to_core => data_trans_from_dma_sig
);
end architecture;
----mapping need to be done yet-------------
-- signal address_bus_sig : std_logic_vector(DATA_SIZE downto 0);
-- -- signal Read_write_enable_sig : std_logic_vector(1 downto 0);
-- signal data_bus_in_sig : std_logic_vector(DATA_SIZE downto 0);
-- signal data_bus_out_sig : std_logic_vector(DATA_SIZE downto 0);
-- signal sent_valid_from_dma_sig : std_logic;
-- signal data_bus_noc_in_sig : std_logic_vector(DATA_SIZE downto 0);
-- signal tx_packet_length_noc_sig : std_logic_vector(LENGTH downto 0);
-- signal rx_packet_length_noc_sig : std_logic_vector(LENGTH downto 0);
-- signal local_noc_tx_sig : std_logic_vector(PACKET downto 0);
-- signal local_vc_write_rx_noc_sig : std_logic;
-- signal receive_valid_to_dma_sig : std_logic;
-- signal sent_ack_to_dma_sig : std_logic_vector(LENGTH downto 0);
-- signal data_bus_noc_out _sig : std_logic_vector(DATA_SIZE downto 0);
-- signal data_trans_from_dma_sig : std_logic_vector(LENGTH downto 0);
-- signal funct_to_dma_sig : std_logic_vector(INST_SIZE downto 0);
-- signal address_to_dma_sig : std_logic_vector(INST_SIZE downto 0);
-- signal size_to_dma_sig : std_logic_vector(LENGTH downto 0);
-- signal rx_packet_length_noc_to_dma_sig : std_logic_vector(LENGTH downto 0);
-- signal receive_valid_to_dma_from_noc_sig : std_logic;
-- signal sent_ack_to_dma_from_noc_sig : std_logic_vector(LENGTH downto 0);
-- signal funct_core_to_dma_sig : std_logic_vector(INST_SIZE downto 0);
-- signal address_core_to_dma_sig : std_logic_vector(INST_SIZE downto 0);
-- Signal size_core_to_dma_sig : std_logic_vector(LENGTH downto 0);
-- signal address_bus_from_dma_sig : std_logic_vector(DATA_SIZE downto 0);
-- -- signal Read_write_enable_from_dma_sig : std_logic_vector(1 downto 0);
-- signal sent_valid_from_dma_to_noc_sig : std_logic;
-- signal tx_packet_length_noc_from_dma_sig : std_logic_vector(LENGTH downto 0);
-- signal data_trans_from_dma_to_core_sig : std_logic_vector(LENGTH downto 0);

107
FULL_DMA_tb.vhd
View file

@ -2,6 +2,7 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.NOC_3D_PACKAGE.all;
use std.env.stop;
-- vcom -work work -2008 -explicit -stats=none D:/project_item_ids/DMA_VHDL/DMA_ARCH_MODULAR_DESGIN/FULL_DMA_tb.vhd
@ -15,10 +16,9 @@ architecture fulldmatb_arch of fulldmatb is
constant LENGTH : natural := 4; -- Define constant for vector size for size of Id's 5 bits
constant PACKET : natural := 31; -- Define constant for vector size for size of packet 32 bits
constant REG_SIZE : natural := 63; -- Define constant for vector size for size of Reg 64 bits
constant DMA_WRITE_TO_RAM : std_logic_vector(6 downto 0) := std_logic_vector(to_unsigned(15, 7)); --"0001111";
constant DMA_READ_TO_RAM : std_logic_vector(6 downto 0) := std_logic_vector(to_unsigned(127, 7)); --"1111111";
---- type flit_vector is array (natural range <>) of std_logic_vector(31 downto 0);
component full_dma is
generic (
DATA_SIZE : natural := 7; -- Define constant for vector size for data of 8 bits
@ -33,7 +33,7 @@ architecture fulldmatb_arch of fulldmatb is
clk : in std_logic;
rst : in std_logic;
local_noc_rx : in std_logic_vector(PACKET downto 0);--- --From Noc
local_vc_write_rx_noc : in std_logic; ---_vector(192-1 downto 0);--From NoC
local_vc_write_rx_noc : in std_logic; --From NoC
local_incr_rx_vec_noc : in std_logic;
cmd_valid : in std_logic; --From Core
cmd_inst_funct : in std_logic_vector(INST_SIZE downto 0); --From Core
@ -49,7 +49,7 @@ architecture fulldmatb_arch of fulldmatb is
cmd_busy : out std_logic; --To Core
cmd_ready : out std_logic; --To Core --always one
local_noc_tx : out std_logic_vector(PACKET downto 0);--- --To NoC
local_vc_write_tx_noc : out std_logic; ---_vector(192-1 downto 0);--To NoC
local_vc_write_tx_noc : out std_logic; --To NoC
local_incr_tx_vec_noc : out std_logic --To NoC
);
end component;
@ -74,8 +74,6 @@ architecture fulldmatb_arch of fulldmatb is
signal local_incr_rx_vec_sig : std_logic_vector(192-1 downto 0) := (others => '0');
signal local_vc_write_tx_sig : std_logic_vector(192-1 downto 0) := (others => '0');
signal local_incr_tx_vec_sig : std_logic_vector(192-1 downto 0) := (others => '0');
signal local_vc_write_tx_noc1 : std_logic;
signal cmd_valid,local_vc_write_tx_noc2 : std_logic;
signal cmd_inst_funct1,cmd_inst_funct2 : std_logic_vector(INST_SIZE downto 0);
@ -90,22 +88,17 @@ architecture fulldmatb_arch of fulldmatb is
signal cmd_rs2_1, cmd_rs2_2 : std_logic_vector(REG_SIZE downto 0);
signal cmd_busy : std_logic;
signal cmd_ready : std_logic;
signal local_tx_sig1, local_tx_sig2 : std_logic_vector(PACKET downto 0);--- --To NoC
signal local_rx_sig1, local_rx_sig2 : std_logic_vector(PACKET downto 0);--- --To NoC
signal local_vc_write_rx_sig1, local_vc_write_rx_sig2 : std_logic;
signal local_vc_write_tx_sig1, local_vc_write_tx_sig2 : std_logic;
signal local_incr_tx_vec_sig1, local_incr_tx_vec_sig2 : std_logic;
signal local_incr_rx_vec_sig1, local_incr_rx_vec_sig2 : std_logic;
signal failed_status_test1 : std_logic := '0';
type ram_array is array (0 to 127 ) of std_logic_vector (DATA_SIZE downto 0);
alias ram_sig1 is <<signal.fulldma_inst1.single_port_ram_inst.ram: ram_array>>;
alias ram_sig2 is <<signal.fulldma_inst2.single_port_ram_inst.ram: ram_array>>;
-- alias ram_sig1 is fulldma_inst1.single_port_ram_inst.ram : ram_array;
begin
-- Component instantiation with a label
fulldma_inst1 : full_dma
@ -116,9 +109,6 @@ begin
port map (
clk => clk_tb,
rst => rst_tb,
-- local_incr_tx_vec_noc => local_incr_tx_vec_sig(1 sll (DEST_ID_inst1 + 1)),
-- local_noc_rx => local_rx_sig(DEST_ID_inst1),
-- local_vc_write_tx_noc => local_vc_write_tx_sig(1 sll (DEST_ID_inst1 + 1)),
local_noc_rx => local_rx_sig1,
local_vc_write_rx_noc => local_vc_write_rx_sig1,
local_incr_rx_vec_noc => local_incr_rx_vec_sig1,
@ -138,9 +128,6 @@ begin
local_noc_tx => local_tx_sig1,
local_vc_write_tx_noc => local_vc_write_tx_sig1,
local_incr_tx_vec_noc => local_incr_tx_vec_sig1
-- local_incr_rx_vec_noc => local_incr_tx_vec_sig(1 sll (SOURCE_ID_inst1 + 1)),
-- local_noc_tx => local_tx_sig(SOURCE_ID_inst1),
-- local_vc_write_rx_noc => local_vc_write_tx_sig(1 sll (SOURCE_ID_inst1 + 1))
);
-- Component instantiation with a label
fulldma_inst2 : full_dma
@ -151,9 +138,6 @@ begin
port map (
clk => clk_tb,
rst => rst_tb,
-- local_incr_tx_vec_noc => local_incr_tx_vec_sig(1 sll (DEST_ID_inst2 + 1)),
-- local_noc_rx => local_rx_sig(DEST_ID_inst2),
-- local_vc_write_tx_noc => local_vc_write_tx_sig(1 sll (DEST_ID_inst2 + 1)),
local_noc_rx => local_rx_sig2,
local_vc_write_rx_noc => local_vc_write_rx_sig2,
local_incr_rx_vec_noc => local_incr_rx_vec_sig2,
@ -173,7 +157,6 @@ begin
local_noc_tx => local_tx_sig2,
local_vc_write_tx_noc => local_vc_write_tx_sig2,
local_incr_tx_vec_noc => local_incr_tx_vec_sig2
);
full_noc_inst1 : full_noc
@ -203,56 +186,113 @@ begin
--rx
local_rx_sig(1) <= local_tx_sig1;
local_vc_write_rx_sig(4) <= local_vc_write_tx_sig1;
local_incr_rx_vec_sig(0) <= local_incr_tx_vec_sig2;--- sig1
--tx
local_rx_sig1 <= local_tx_sig(1);
local_vc_write_rx_sig1 <= local_vc_write_tx_sig(4);
local_incr_rx_vec_sig1 <= local_incr_tx_vec_sig(4);
--inst2 [rx_dma <= tx_noc] & [rx_noc <= tx_dma] source zero[0]
-- rx
local_rx_sig(0) <= local_tx_sig2;
local_vc_write_rx_sig(0) <= local_vc_write_tx_sig2;
local_incr_rx_vec_sig(4) <= local_incr_tx_vec_sig1;--- sig2
--tx destination one[1]
local_rx_sig2 <= local_tx_sig(0);
local_vc_write_rx_sig2 <= local_vc_write_tx_sig(0);
local_incr_rx_vec_sig2 <= local_incr_tx_vec_sig(0);
-- Simulation process to assign values to CtrlCommand
simproc: process
begin
-- local_vc_write_tx_noc2 <= '0';
cmd_valid <= '0';
rst_tb <= '0';
wait for 10 ns;
rst_tb <= '1';
wait for 40 ns;
-----------------------------------------------Test1---------------------------------------------------
cmd_inst_funct2 <= "0011110"; --#define DMA_WRITE_TO_RAM 30 /// 0X1E
cmd_inst_funct1 <= "0011111"; --#define DMA_READ_FROM_RAM 31 /// 0X1F
cmd_rs1_1 <= std_logic_vector(to_unsigned(0, 57)) & "0000010"; --7 bit address & 57 bit zeros
cmd_rs1_2 <= std_logic_vector(to_unsigned(0, 57)) & "0001000"; --7 bit address & 57 bit zeros
cmd_rs2_1 <= std_logic_vector(to_unsigned(0, 59)) & "00100"; --5 bit size & 59 bit zeros
cmd_rs2_2 <= std_logic_vector(to_unsigned(0, 59)) & "00100"; --5 bit size & 59 bit zeros
cmd_rs2_1 <= std_logic_vector(to_unsigned(0, 59)) & "11100"; --5 bit size & 59 bit zeros
cmd_rs2_2 <= std_logic_vector(to_unsigned(0, 59)) & "11100"; --5 bit size & 59 bit zeros
wait for 20 ns;
cmd_valid <= '1';
wait for 40 ns;
cmd_valid <= '0';
-- local_vc_write_tx_noc2 <= '1';
wait for 180 ns;
-- local_vc_write_tx_noc2 <= '0';
for i in 0 to to_integer(unsigned(cmd_rs2_1)) loop
if(ram_sig1(to_integer(unsigned(cmd_rs1_1)) + i ) /= ram_sig2(to_integer(unsigned(cmd_rs1_2)) + i)) then
report "Test is failed: memory elements are not equal at location " &
report "Test1 is failed: memory elements are not equal at location " &
"cmd_rs1_1 = " & integer'image(to_integer(unsigned(cmd_rs1_1)+i)) &
", cmd_rs1_2 = " & integer'image(to_integer(unsigned(cmd_rs1_2)+i))
severity note;
failed_status_test1 <= '1';
exit; -- Exit the loop
stop;--exit; -- Exit the loop
end if;
end loop;
wait for 200 ns;--200
----------------------------------------------Test2------------------------------------------------------
cmd_inst_funct1 <= "0011110"; --#define DMA_WRITE_TO_RAM 30 /// 0X1E
cmd_inst_funct2 <= "0011111"; --#define DMA_READ_FROM_RAM 31 /// 0X1F
cmd_rs1_2 <= std_logic_vector(to_unsigned(0, 57)) & "0000101"; --7 bit address & 57 bit zeros
cmd_rs1_1 <= std_logic_vector(to_unsigned(0, 57)) & "0001101"; --7 bit address & 57 bit zeros
cmd_rs2_2 <= std_logic_vector(to_unsigned(0, 59)) & "00100"; --5 bit size & 59 bit zeros
cmd_rs2_1 <= std_logic_vector(to_unsigned(0, 59)) & "00100"; --5 bit size & 59 bit zeros
wait for 20 ns;
cmd_valid <= '1';
wait for 40 ns;
cmd_valid <= '0';
wait for 180 ns;
for i in 0 to to_integer(unsigned(cmd_rs2_1)) loop
if(ram_sig1(to_integer(unsigned(cmd_rs1_1)) + i ) /= ram_sig2(to_integer(unsigned(cmd_rs1_2)) + i)) then
report "Test2 is failed: memory elements are not equal at location " &
"cmd_rs1_1 = " & integer'image(to_integer(unsigned(cmd_rs1_1)+i)) &
", cmd_rs1_2 = " & integer'image(to_integer(unsigned(cmd_rs1_2)+i))
severity note;
failed_status_test1 <= '1';
stop;--exit; -- Exit the loop
end if;
end loop;
wait for 100 ns;
----------------------------------------------Test3------------------------------------------------------
cmd_inst_funct1 <= "0011110"; --#define DMA_WRITE_TO_RAM 30 /// 0X1E
cmd_inst_funct2 <= "0011111"; --#define DMA_READ_FROM_RAM 31 /// 0X1F
cmd_rs1_2 <= std_logic_vector(to_unsigned(0, 57)) & "0001101"; --7 bit address & 57 bit zeros
cmd_rs1_1 <= std_logic_vector(to_unsigned(0, 57)) & "0010101"; --7 bit address & 57 bit zeros
cmd_rs2_2 <= std_logic_vector(to_unsigned(0, 59)) & "01100"; --5 bit size & 59 bit zeros
cmd_rs2_1 <= std_logic_vector(to_unsigned(0, 59)) & "01100"; --5 bit size & 59 bit zeros
wait for 20 ns;
cmd_valid <= '1';
wait for 40 ns;
cmd_valid <= '0';
wait for 180 ns;
for i in 0 to to_integer(unsigned(cmd_rs2_1)) loop
if(ram_sig1(to_integer(unsigned(cmd_rs1_1)) + i ) /= ram_sig2(to_integer(unsigned(cmd_rs1_2)) + i)) then
report "Test3 is failed: memory elements are not equal at location " &
"cmd_rs1_1 = " & integer'image(to_integer(unsigned(cmd_rs1_1)+i)) &
", cmd_rs1_2 = " & integer'image(to_integer(unsigned(cmd_rs1_2)+i))
severity note;
failed_status_test1 <= '1';
stop;--exit; -- Exit the loop
end if;
end loop;
@ -260,14 +300,11 @@ begin
--------------------------------------------------------------------------------------------------------------
if failed_status_test1 = '0' then
report "Test is passed: memory elements are equal starting locations " &
report "All Test's are passed: memory elements are equal starting locations " &
"cmd_rs1_1 = " & integer'image(to_integer(unsigned(cmd_rs1_1))) &
", cmd_rs1_2 = " & integer'image(to_integer(unsigned(cmd_rs1_2)))
severity note;
end if;
wait for 1000 ns;
-- -- wait for 1000 ns ;
end process;
end architecture;

17
NoC_INTERFACE.vhd
View file

@ -11,10 +11,6 @@ use ieee.numeric_std.all;
----------------------NoC Interface Entity---------------------------
entity noc_interface is
-- constant DATA_SIZE : integer := 7; -- Define constant for vector size for data of 8 bits
-- constant LENGTH : integer := 4; -- Define constant for vector size for size of Id's 5 bits
-- constant PACKET : integer := 11; -- Define constant for vector size for size of Id's 12 bits
-- constant REG_SIZE : integer := 31; -- Define constant for vector size for size of Reg 31 bits
generic (
DATA_SIZE : natural := 7; -- Define constant for vector size for data of 8 bits
LENGTH : natural := 4; -- Define constant for vector size for size of Id's 5 bits
@ -49,10 +45,6 @@ architecture noc_interface_arch of noc_interface is
signal count : std_logic_vector(LENGTH downto 0);
signal sent_packet : std_logic_vector(LENGTH downto 0);
signal packet_len : std_logic_vector(LENGTH downto 0);
--signal packet_length : std_logic_vector(4 downto 0);
begin
rxprocess : process(clk, rst)
begin
@ -60,7 +52,7 @@ begin
rx_packet_length_noc <= (others => '0');
local_noc_tx <= (others => '0');
local_vc_write_tx_noc <= '0';
--local_incr_tx_vec_noc <= '0';
local_incr_tx_vec_noc <= '0';-----
receive_valid_to_dma <= '0';
sent_ack_to_dma <= (others => '0');
data_bus_noc_out <= (others => '0');
@ -80,25 +72,28 @@ begin
count <= (others => '0'); --counter reset
packet_id <= local_noc_rx(28 downto 17); --current packetid
receive_valid_to_dma <= '1';
local_incr_tx_vec_noc <= '1';-------
elsif(unsigned(count) <= unsigned(packet_len) and unsigned(packet_len) > 0) then
report "receive_valid_to_dma is 1 from Line 80";
receive_valid_to_dma <= '1'; --valid to DMA
count <= std_logic_vector(unsigned(count) + 1); --counter update
data_bus_noc_out <= local_noc_rx(DATA_SIZE downto 0 ); --NoC is given to RAM
local_incr_tx_vec_noc <= '1';-------
else
report "receive_valid_to_dma is 0 from Line 86";
packet_len <= (others=>'0');
receive_valid_to_dma <= '0';
data_bus_noc_out <= (others=>'0');
count <= (others=>'0');
local_incr_tx_vec_noc <= '0';-------
end if;
--------------------Writing to NoC----------------------------------
elsif ((sent_valid_from_dma = '1') and (to_integer(unsigned(tx_packet_length_noc)) >= 0)) then -- the valid from dma is one cycle behind
if(sent_packet = "00000") then
--sent_ack_to_dma <= std_logic_vector(unsigned(sent_packet) + 1); --to DMA updated value
sent_packet <= std_logic_vector(unsigned(sent_packet) + 1);
--updating packet id
local_noc_tx <= "100" & packet_id & SOURCE_ID & DEST_ID & tx_packet_length_noc;
@ -113,7 +108,7 @@ begin
rx_packet_length_noc <= (others => '0');
local_noc_tx <= (others => '0');
local_vc_write_tx_noc <= '0';
---local_incr_tx_vec_noc <= '0';
local_incr_tx_vec_noc <= '0';---
receive_valid_to_dma <= '0';
sent_ack_to_dma <= (others => '0');
data_bus_noc_out <= (others => '0');

23
ROCC_INTERFACE.vhd
View file

@ -11,10 +11,6 @@ use ieee.numeric_std.all;
----------------------RoCC Interface Entity---------------------------
entity rocc_interface is
-- constant INST_SIZE : integer := 6; -- Define constant for vector size for inst of 6 bits
-- constant LENGTH : integer := 4; -- Define constant for vector size for size of Id's 5 bits
-- constant PACKET : integer := 11; -- Define constant for vector size for size of Id's 12 bits
-- constant REG_SIZE : integer := 63; -- Define constant for vector size for size of Reg 63 bits
generic (
DMA_WRITE_TO_RAM : std_logic_vector(6 downto 0) := "0001111";
DMA_READ_TO_RAM : std_logic_vector(6 downto 0) := "1111111";
@ -55,8 +51,6 @@ architecture rocc_interface_arch of rocc_interface is
signal cmd_rs2_sig : std_logic_vector(REG_SIZE downto 0);
Signal cmd_inst_funct_sig : std_logic_vector(INST_SIZE downto 0);
Signal cmd_valid_sig : std_logic;
--signal Sent_packet : std_logic_vector(4 downto 0);
--signal packet_length : std_logic_vector(4 downto 0);
begin
process(clk, rst)
@ -70,33 +64,38 @@ begin
size_to_dma <= (others => '0');
cmd_rs1_sig <= (others => '0');
cmd_rs2_sig <= (others => '0');
cmd_inst_funct_sig <= (others => '0');
cmd_inst_funct_sig <= (others => '0');---
elsif rising_edge(clk) then
--------------------Send to the DMA--------------------------------
if((cmd_valid_sig = '1') and (cmd_rs2_sig(LENGTH downto 0) > data_trans_from_dma)) then
if cmd_inst_funct = std_logic_vector(to_unsigned(CORE_WRITE_FUNC, 7)) then --#define DMA_WRITE_TO_RAM 30 /// 0X1E
if((cmd_valid_sig = '1') and (to_integer(unsigned(cmd_rs2_sig(LENGTH downto 0))) > (to_integer(unsigned(data_trans_from_dma))+1))) then
if cmd_inst_funct_sig = std_logic_vector(to_unsigned(CORE_WRITE_FUNC, 7)) then --#define DMA_WRITE_TO_RAM 30 /// 0X1E
funct_to_dma <= DMA_WRITE_TO_RAM;
elsif cmd_inst_funct = std_logic_vector(to_unsigned(CORE_READ_FUNC, 7))then--"001111" then --#define DMA_READ_FROM_RAM 31 /// 0X1F
elsif cmd_inst_funct_sig = std_logic_vector(to_unsigned(CORE_READ_FUNC, 7))then--"001111" then --#define DMA_READ_FROM_RAM 31 /// 0X1F
funct_to_dma <= DMA_READ_TO_RAM;
else
funct_to_dma <= (others => '0');
end if;
address_to_dma <= cmd_rs1_sig(INST_SIZE downto 0);
size_to_dma <= cmd_rs2_sig(LENGTH downto 0);
cmd_busy <= '1';
--------------------Reading from RoCC--------------------------------
elsif (cmd_valid = '1') then
elsif (cmd_valid = '1' and (to_integer(unsigned(data_trans_from_dma)) = 0)) then
cmd_rs1_sig <= cmd_rs1;
cmd_rs2_sig <= cmd_rs2; --size 4 downto 0 [5bits]
cmd_inst_funct_sig <= cmd_inst_funct;
cmd_inst_funct_sig <= cmd_inst_funct;----
cmd_valid_sig <= '1';
cmd_busy <= '1';
else
cmd_valid_sig <= '0';
cmd_busy <= '0';
cmd_rs1_sig <= (others => '0');
cmd_rs1_sig <= (others => '0');
funct_to_dma <= (others => '0');
cmd_inst_funct_sig <= (others => '0');
end if;

10
SINGLE_PORT_RAM.vhd
View file

@ -2,14 +2,12 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
----------------------ram Entity---------------------------
----------------------------------------ram Entity---------------------------------------------------
entity single_port_ram is
generic (
DATA_SIZE : natural := 7; -- Default source ID should be changed
ADDRESS_SIZE : natural := 6 -- Default destination ID should be changed
);
--constant DATA_SIZE : integer := 7; -- Define constant for vector size for data of 8 bits
--constant ADDRESS_SIZE : integer := 6; -- Define constant for vector size for address 7 bits
port(
clk : in std_logic;
rst : in std_logic;
@ -21,15 +19,13 @@ entity single_port_ram is
);
end entity;
----------------------ram Behaviour------------------------
----------------------------------------ram Behaviour--------------------------------------------------
architecture single_port_ram_behav of single_port_ram is
------- define the new type for the 128x8 ram
type ram_array is array (0 to 127 ) of std_logic_vector (DATA_SIZE downto 0);
-------- initial values in the ram to X00
signal ram: ram_array := (others=>x"00");
signal initialized : std_logic; -- Initialization flag
begin
process(clk, rst)
begin
@ -46,7 +42,7 @@ begin
initialized <= '0';
end if;
-- synthesis translate_on
--Read Write functionality of ram
if (read_enable = '1' and write_enable = '0' )then --read enable; [MSB] READ Enable [LSB] WRITE Enable
data_bus_out <= ram(to_integer(unsigned(address_bus(ADDRESS_SIZE downto 0 )))); -- read data from ram
elsif (read_enable = '0' and write_enable = '1') then --write enable; [MSB] READ Enable [LSB] WRITE Enable