final working full DMA module
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eceea6c381
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13ab5916b4
6 changed files with 149 additions and 204 deletions
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@ -4,9 +4,6 @@ use ieee.numeric_std.all;
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----------------------DMA Controller Entity---------------------------
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entity dma_controller is
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-- constant DATA_SIZE : integer := 7; -- Define constant for vector size for data of 8 bits
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-- constant ADDRESS_SIZE : integer := 6; -- Define constant for vector size for address 7 bits
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-- constant ID_SIZE : integer := 4; -- Define constant for vector size for size of Id's 5 bits
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generic (
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RAM_WRITE_CMD : natural := 15; -- Writing to ram command from rocc
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RAM_READ_CMD : natural := 127; -- Reading from ram command from rocc
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@ -35,11 +32,8 @@ end entity;
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----------------------DMA Controller Behaviour------------------------
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architecture dma_controller_arch of dma_controller is
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--Signal count_from_noc : std_logic_vector(ID_SIZE downto 0);
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Signal count_to_noc : std_logic_vector(ID_SIZE downto 0);
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Signal address_to_ram : std_logic_vector(ADDRESS_SIZE downto 0);
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begin
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process(clk, rst)
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begin
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@ -50,71 +44,64 @@ begin
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address_bus_from_dma <= (others => '0');
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tx_packet_length_noc_from_dma <= (others => '0');
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data_trans_from_dma_to_core <= (others => '0');
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-- count_from_noc <= (others => '0');
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count_to_noc <= (others => '0');
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address_to_ram <= (others => '0');
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elsif rising_edge(clk) then
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----------------------Writing to RAM from NOC------------------------
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if funct_core_to_dma = std_logic_vector(to_unsigned(RAM_WRITE_CMD, DATA_SIZE)) then --- x"0f" 15 Its arbitarly choosen from RoCC_Interface
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if unsigned(count_to_noc) < (unsigned(size_core_to_dma)) then --+10 will reproduce same valid signal comparing rx_packet_length_noc_to_dma = size_core_to_dma
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if funct_core_to_dma = std_logic_vector(to_unsigned(RAM_WRITE_CMD, DATA_SIZE)) then --- x"0f" 15 Its arbitarly choosen from RoCC_Interface
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if unsigned(count_to_noc) < (unsigned(size_core_to_dma)) then
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if count_to_noc = "00000" then ---count_from_noc but not working in the wave simulation
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address_to_ram <= address_core_to_dma;
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count_to_noc <= std_logic_vector(unsigned(count_to_noc) + 1);
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--write_enable_from_dma <= '1'; --Write Enable
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--end if;
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address_to_ram <= address_core_to_dma;
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count_to_noc <= std_logic_vector(unsigned(count_to_noc) + 1);
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elsif receive_valid_to_dma_from_noc = '1' then
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address_bus_from_dma <= address_to_ram;
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--report "write_enable_from_dma is 1 from Line 68";
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write_enable_from_dma <= '1'; --Write Enable ----<<<<Why the value is not updateded>>>>
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write_enable_from_dma <= '1'; --Write Enable
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read_enable_from_dma <= '0'; --'0'
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data_trans_from_dma_to_core <= count_to_noc ;-- std_logic_vector(unsigned(count_to_noc) - 1)
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address_to_ram <= std_logic_vector(unsigned(address_to_ram) + 1);
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count_to_noc <= std_logic_vector(unsigned(count_to_noc) + 1);
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else
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----report "write_enable_from_dma is 0 from Line 75";
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write_enable_from_dma <= '0'; --Write Enable ----<<<<Why the value is not updateded>>>>
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write_enable_from_dma <= '0'; --Write Enable
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read_enable_from_dma <= '0'; --'0'
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end if;
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else
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----report "write_enable_from_dma is 0 from Line 75";
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write_enable_from_dma <= '0'; --Write Enable ----<<<<Why the value is not updateded>>>>
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write_enable_from_dma <= '0'; --Write Enable
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read_enable_from_dma <= '0'; --'0'
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count_to_noc <= (others => '0');
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data_trans_from_dma_to_core <= (others => '0');
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end if;
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-- else
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-- count_from_noc <= (others => '0');
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-- read_enable_from_dma <= '0';
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-- write_enable_from_dma <= 'Z';--'0';
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-- sent_valid_from_dma_to_noc <= '0';
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-- end if;
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----------------------Reading from RAM to NOC------------------------
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elsif funct_core_to_dma = std_logic_vector(to_unsigned(RAM_READ_CMD, DATA_SIZE)) then --- x"7f" 127 Its arbitarly choosen from RoCC_Interface
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if unsigned(count_to_noc) < unsigned(size_core_to_dma) then --sent_ack_to_dma_from_noc could be used instead of the count to Noc
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if unsigned(count_to_noc) < unsigned(size_core_to_dma) then
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if count_to_noc = "00000" then
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address_to_ram <= address_core_to_dma;
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tx_packet_length_noc_from_dma <= size_core_to_dma; --giving the size to the header of the NoC flit
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count_to_noc <= std_logic_vector(unsigned(count_to_noc) + 1);
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---sent_valid_from_dma_to_noc <= '1';
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else
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address_bus_from_dma <= address_to_ram;
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write_enable_from_dma <= '0';
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read_enable_from_dma <= '1'; --Read Enable
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data_trans_from_dma_to_core <= sent_ack_to_dma_from_noc;
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data_trans_from_dma_to_core <= count_to_noc;--sent_ack_to_dma_from_noc;
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address_to_ram <= std_logic_vector(unsigned(address_to_ram) + 1);
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count_to_noc <= std_logic_vector(unsigned(count_to_noc) + 1);
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sent_valid_from_dma_to_noc <= '1';
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end if;
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elsif unsigned(count_to_noc) < (unsigned(size_core_to_dma)+2) then
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count_to_noc <= std_logic_vector(unsigned(count_to_noc) + 1);
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sent_valid_from_dma_to_noc <= '1';
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count_to_noc <= std_logic_vector(unsigned(count_to_noc) + 1);
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sent_valid_from_dma_to_noc <= '1';
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else
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read_enable_from_dma <= '0';
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write_enable_from_dma <= '0';
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sent_valid_from_dma_to_noc <= '0';
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read_enable_from_dma <= '0';
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write_enable_from_dma <= '0';
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sent_valid_from_dma_to_noc <= '0';
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count_to_noc <= (others => '0');
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end if;
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else
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count_to_noc <= (others => '0');
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@ -122,6 +109,7 @@ begin
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--report "write_enable_from_dma is 0 from Line 111";
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write_enable_from_dma <= '0';
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sent_valid_from_dma_to_noc <= '0';
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data_trans_from_dma_to_core <= (others => '0');
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end if;
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end if;
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end process;
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86
FULL_DMA.vhd
86
FULL_DMA.vhd
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@ -2,13 +2,9 @@ library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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----------------------Full DMA Entity---------------------------
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----------------------------------------Full DMA Entity-------------------------------------------
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entity full_dma is
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-- constant DATA_SIZE : integer := 7; -- Define constant for vector size for data of 8 bits
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-- constant INST_SIZE : integer := 6; -- Define constant for vector size for inst of 6 bits
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-- constant LENGTH : integer := 4; -- Define constant for vector size for size of Id's 5 bits
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-- constant PACKET : integer := 31; -- Define constant for vector size for size of packet 32 bits
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-- constant REG_SIZE : integer := 63; -- Define constant for vector size for size of Reg 64 bits
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generic (
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DATA_SIZE : natural := 7; -- Define constant for vector size for data of 8 bits
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INST_SIZE : natural := 6; -- Define constant for vector size for inst of 6 bits
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@ -22,7 +18,7 @@ entity full_dma is
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clk : in std_logic;
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rst : in std_logic;
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local_noc_rx : in std_logic_vector(PACKET downto 0);--- --From Noc
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local_vc_write_rx_noc : in std_logic; ---_vector(192-1 downto 0);--From NoC
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local_vc_write_rx_noc : in std_logic; --From NoC
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local_incr_rx_vec_noc : in std_logic;
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cmd_valid : in std_logic; --From Core
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cmd_inst_funct : in std_logic_vector(INST_SIZE downto 0); --From Core
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@ -38,12 +34,12 @@ entity full_dma is
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cmd_busy : out std_logic; --To Core
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cmd_ready : out std_logic; --To Core --always one
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local_noc_tx : out std_logic_vector(PACKET downto 0);--- --To NoC
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local_vc_write_tx_noc : out std_logic; ---_vector(192-1 downto 0);--To NoC
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local_vc_write_tx_noc : out std_logic; --To NoC
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local_incr_tx_vec_noc : out std_logic --To NoC
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);
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end entity;
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----------------------Full DMA Behaviour------------------------
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----------------------------------------Full DMA Behaviour-------------------------------------------
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architecture full_dma_arch of full_dma is
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component single_port_ram is
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@ -69,15 +65,15 @@ architecture full_dma_arch of full_dma is
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data_bus_noc_in : in std_logic_vector(DATA_SIZE downto 0); --From RAM
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tx_packet_length_noc : in std_logic_vector(LENGTH downto 0); --From DMA
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local_noc_rx : in std_logic_vector(REG_SIZE downto 0);--- --From Noc
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local_vc_write_rx_noc: in std_logic; ---_vector(192-1 downto 0); --From NoC
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local_vc_write_rx_noc: in std_logic; --From NoC
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local_incr_rx_vec_noc: in std_logic; --From NoC
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rx_packet_length_noc : out std_logic_vector(LENGTH downto 0); --To DMA
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local_noc_tx : out std_logic_vector(REG_SIZE downto 0);--- --To NoC
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local_vc_write_tx_noc: out std_logic; ---_vector(192-1 downto 0); --To NoC
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local_vc_write_tx_noc: out std_logic; --To NoC
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local_incr_tx_vec_noc: out std_logic; --To NoC
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receive_valid_to_dma : out std_logic; --To DMA
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sent_ack_to_dma : out std_logic_vector(LENGTH downto 0);--------- --To DMA
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data_bus_noc_out : out std_logic_vector(DATA_SIZE downto 0) --To RAM
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data_bus_noc_out : out std_logic_vector(DATA_SIZE downto 0) --To RAM
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);
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end component;
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component rocc_interface is
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@ -126,46 +122,18 @@ architecture full_dma_arch of full_dma is
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signal address_bus_sig : std_logic_vector(INST_SIZE downto 0);
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signal read_enable_sig : std_logic;
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signal write_enable_sig : std_logic;
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-- signal Read_write_enable_sig : std_logic_vector(1 downto 0);
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signal data_bus_in_sig : std_logic_vector(DATA_SIZE downto 0);
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signal data_bus_out_sig : std_logic_vector(DATA_SIZE downto 0);
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signal sent_valid_from_dma_sig : std_logic;
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--signal data_bus_noc_in_sig : std_logic_vector(DATA_SIZE downto 0);
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signal tx_packet_length_noc_sig : std_logic_vector(LENGTH downto 0);
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signal rx_packet_length_noc_sig : std_logic_vector(LENGTH downto 0);
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--signal local_noc_tx_sig : std_logic_vector(PACKET downto 0);
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--signal local_vc_write_rx_noc_sig : std_logic;
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signal receive_valid_to_dma_sig : std_logic;
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signal sent_ack_to_dma_sig : std_logic_vector(LENGTH downto 0);
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--signal data_bus_noc_out _sig : std_logic_vector(DATA_SIZE downto 0);
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signal data_trans_from_dma_sig : std_logic_vector(LENGTH downto 0);
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signal funct_to_dma_sig : std_logic_vector(INST_SIZE downto 0);
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signal address_to_dma_sig : std_logic_vector(INST_SIZE downto 0);
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signal size_to_dma_sig : std_logic_vector(LENGTH downto 0);
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--signal rx_packet_length_noc_to_dma_sig : std_logic_vector(LENGTH downto 0);
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-- signal receive_valid_to_dma_from_noc_sig : std_logic;
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--signal sent_ack_to_dma_from_noc_sig : std_logic_vector(LENGTH downto 0);
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--signal funct_core_to_dma_sig : std_logic_vector(INST_SIZE downto 0);
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--signal address_core_to_dma_sig : std_logic_vector(INST_SIZE downto 0);
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--Signal size_core_to_dma_sig : std_logic_vector(LENGTH downto 0);
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--signal address_bus_from_dma_sig : std_logic_vector(DATA_SIZE downto 0);
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-- signal Read_write_enable_from_dma_sig : std_logic_vector(1 downto 0);
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--signal sent_valid_from_dma_to_noc_sig : std_logic;
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--signal tx_packet_length_noc_from_dma_sig : std_logic_vector(LENGTH downto 0);
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--signal data_trans_from_dma_to_core_sig : std_logic_vector(LENGTH downto 0);
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begin
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-- Single_Port_RAM mapping
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single_port_ram_inst : single_port_ram
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@ -179,7 +147,6 @@ architecture full_dma_arch of full_dma is
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data_bus_out => data_bus_out_sig
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);
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-- Noc_Interface mapping
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noc_interface_inst : noc_interface
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generic map (
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@ -246,43 +213,6 @@ architecture full_dma_arch of full_dma is
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tx_packet_length_noc_from_dma => tx_packet_length_noc_sig,
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data_trans_from_dma_to_core => data_trans_from_dma_sig
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);
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end architecture;
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----mapping need to be done yet-------------
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-- signal address_bus_sig : std_logic_vector(DATA_SIZE downto 0);
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-- -- signal Read_write_enable_sig : std_logic_vector(1 downto 0);
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-- signal data_bus_in_sig : std_logic_vector(DATA_SIZE downto 0);
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-- signal data_bus_out_sig : std_logic_vector(DATA_SIZE downto 0);
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-- signal sent_valid_from_dma_sig : std_logic;
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-- signal data_bus_noc_in_sig : std_logic_vector(DATA_SIZE downto 0);
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-- signal tx_packet_length_noc_sig : std_logic_vector(LENGTH downto 0);
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-- signal rx_packet_length_noc_sig : std_logic_vector(LENGTH downto 0);
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-- signal local_noc_tx_sig : std_logic_vector(PACKET downto 0);
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-- signal local_vc_write_rx_noc_sig : std_logic;
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-- signal receive_valid_to_dma_sig : std_logic;
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-- signal sent_ack_to_dma_sig : std_logic_vector(LENGTH downto 0);
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-- signal data_bus_noc_out _sig : std_logic_vector(DATA_SIZE downto 0);
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-- signal data_trans_from_dma_sig : std_logic_vector(LENGTH downto 0);
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-- signal funct_to_dma_sig : std_logic_vector(INST_SIZE downto 0);
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-- signal address_to_dma_sig : std_logic_vector(INST_SIZE downto 0);
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-- signal size_to_dma_sig : std_logic_vector(LENGTH downto 0);
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-- signal rx_packet_length_noc_to_dma_sig : std_logic_vector(LENGTH downto 0);
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-- signal receive_valid_to_dma_from_noc_sig : std_logic;
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-- signal sent_ack_to_dma_from_noc_sig : std_logic_vector(LENGTH downto 0);
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-- signal funct_core_to_dma_sig : std_logic_vector(INST_SIZE downto 0);
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-- signal address_core_to_dma_sig : std_logic_vector(INST_SIZE downto 0);
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-- Signal size_core_to_dma_sig : std_logic_vector(LENGTH downto 0);
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-- signal address_bus_from_dma_sig : std_logic_vector(DATA_SIZE downto 0);
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-- -- signal Read_write_enable_from_dma_sig : std_logic_vector(1 downto 0);
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-- signal sent_valid_from_dma_to_noc_sig : std_logic;
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-- signal tx_packet_length_noc_from_dma_sig : std_logic_vector(LENGTH downto 0);
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-- signal data_trans_from_dma_to_core_sig : std_logic_vector(LENGTH downto 0);
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107
FULL_DMA_tb.vhd
107
FULL_DMA_tb.vhd
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@ -2,6 +2,7 @@ library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.NOC_3D_PACKAGE.all;
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use std.env.stop;
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-- vcom -work work -2008 -explicit -stats=none D:/project_item_ids/DMA_VHDL/DMA_ARCH_MODULAR_DESGIN/FULL_DMA_tb.vhd
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@ -15,10 +16,9 @@ architecture fulldmatb_arch of fulldmatb is
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constant LENGTH : natural := 4; -- Define constant for vector size for size of Id's 5 bits
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constant PACKET : natural := 31; -- Define constant for vector size for size of packet 32 bits
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constant REG_SIZE : natural := 63; -- Define constant for vector size for size of Reg 64 bits
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constant DMA_WRITE_TO_RAM : std_logic_vector(6 downto 0) := std_logic_vector(to_unsigned(15, 7)); --"0001111";
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constant DMA_READ_TO_RAM : std_logic_vector(6 downto 0) := std_logic_vector(to_unsigned(127, 7)); --"1111111";
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---- type flit_vector is array (natural range <>) of std_logic_vector(31 downto 0);
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component full_dma is
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generic (
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DATA_SIZE : natural := 7; -- Define constant for vector size for data of 8 bits
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@ -33,7 +33,7 @@ architecture fulldmatb_arch of fulldmatb is
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clk : in std_logic;
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rst : in std_logic;
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local_noc_rx : in std_logic_vector(PACKET downto 0);--- --From Noc
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local_vc_write_rx_noc : in std_logic; ---_vector(192-1 downto 0);--From NoC
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local_vc_write_rx_noc : in std_logic; --From NoC
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local_incr_rx_vec_noc : in std_logic;
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cmd_valid : in std_logic; --From Core
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cmd_inst_funct : in std_logic_vector(INST_SIZE downto 0); --From Core
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@ -49,7 +49,7 @@ architecture fulldmatb_arch of fulldmatb is
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cmd_busy : out std_logic; --To Core
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cmd_ready : out std_logic; --To Core --always one
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local_noc_tx : out std_logic_vector(PACKET downto 0);--- --To NoC
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local_vc_write_tx_noc : out std_logic; ---_vector(192-1 downto 0);--To NoC
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local_vc_write_tx_noc : out std_logic; --To NoC
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local_incr_tx_vec_noc : out std_logic --To NoC
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);
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end component;
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@ -74,8 +74,6 @@ architecture fulldmatb_arch of fulldmatb is
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signal local_incr_rx_vec_sig : std_logic_vector(192-1 downto 0) := (others => '0');
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signal local_vc_write_tx_sig : std_logic_vector(192-1 downto 0) := (others => '0');
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signal local_incr_tx_vec_sig : std_logic_vector(192-1 downto 0) := (others => '0');
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signal local_vc_write_tx_noc1 : std_logic;
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signal cmd_valid,local_vc_write_tx_noc2 : std_logic;
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signal cmd_inst_funct1,cmd_inst_funct2 : std_logic_vector(INST_SIZE downto 0);
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@ -90,22 +88,17 @@ architecture fulldmatb_arch of fulldmatb is
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signal cmd_rs2_1, cmd_rs2_2 : std_logic_vector(REG_SIZE downto 0);
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signal cmd_busy : std_logic;
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signal cmd_ready : std_logic;
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|
||||
signal local_tx_sig1, local_tx_sig2 : std_logic_vector(PACKET downto 0);--- --To NoC
|
||||
signal local_rx_sig1, local_rx_sig2 : std_logic_vector(PACKET downto 0);--- --To NoC
|
||||
signal local_vc_write_rx_sig1, local_vc_write_rx_sig2 : std_logic;
|
||||
signal local_vc_write_tx_sig1, local_vc_write_tx_sig2 : std_logic;
|
||||
signal local_incr_tx_vec_sig1, local_incr_tx_vec_sig2 : std_logic;
|
||||
signal local_incr_rx_vec_sig1, local_incr_rx_vec_sig2 : std_logic;
|
||||
|
||||
signal failed_status_test1 : std_logic := '0';
|
||||
type ram_array is array (0 to 127 ) of std_logic_vector (DATA_SIZE downto 0);
|
||||
alias ram_sig1 is <<signal.fulldma_inst1.single_port_ram_inst.ram: ram_array>>;
|
||||
alias ram_sig2 is <<signal.fulldma_inst2.single_port_ram_inst.ram: ram_array>>;
|
||||
|
||||
-- alias ram_sig1 is fulldma_inst1.single_port_ram_inst.ram : ram_array;
|
||||
|
||||
|
||||
begin
|
||||
-- Component instantiation with a label
|
||||
fulldma_inst1 : full_dma
|
||||
|
|
@ -116,9 +109,6 @@ begin
|
|||
port map (
|
||||
clk => clk_tb,
|
||||
rst => rst_tb,
|
||||
-- local_incr_tx_vec_noc => local_incr_tx_vec_sig(1 sll (DEST_ID_inst1 + 1)),
|
||||
-- local_noc_rx => local_rx_sig(DEST_ID_inst1),
|
||||
-- local_vc_write_tx_noc => local_vc_write_tx_sig(1 sll (DEST_ID_inst1 + 1)),
|
||||
local_noc_rx => local_rx_sig1,
|
||||
local_vc_write_rx_noc => local_vc_write_rx_sig1,
|
||||
local_incr_rx_vec_noc => local_incr_rx_vec_sig1,
|
||||
|
|
@ -138,9 +128,6 @@ begin
|
|||
local_noc_tx => local_tx_sig1,
|
||||
local_vc_write_tx_noc => local_vc_write_tx_sig1,
|
||||
local_incr_tx_vec_noc => local_incr_tx_vec_sig1
|
||||
-- local_incr_rx_vec_noc => local_incr_tx_vec_sig(1 sll (SOURCE_ID_inst1 + 1)),
|
||||
-- local_noc_tx => local_tx_sig(SOURCE_ID_inst1),
|
||||
-- local_vc_write_rx_noc => local_vc_write_tx_sig(1 sll (SOURCE_ID_inst1 + 1))
|
||||
);
|
||||
-- Component instantiation with a label
|
||||
fulldma_inst2 : full_dma
|
||||
|
|
@ -151,9 +138,6 @@ begin
|
|||
port map (
|
||||
clk => clk_tb,
|
||||
rst => rst_tb,
|
||||
-- local_incr_tx_vec_noc => local_incr_tx_vec_sig(1 sll (DEST_ID_inst2 + 1)),
|
||||
-- local_noc_rx => local_rx_sig(DEST_ID_inst2),
|
||||
-- local_vc_write_tx_noc => local_vc_write_tx_sig(1 sll (DEST_ID_inst2 + 1)),
|
||||
local_noc_rx => local_rx_sig2,
|
||||
local_vc_write_rx_noc => local_vc_write_rx_sig2,
|
||||
local_incr_rx_vec_noc => local_incr_rx_vec_sig2,
|
||||
|
|
@ -173,7 +157,6 @@ begin
|
|||
local_noc_tx => local_tx_sig2,
|
||||
local_vc_write_tx_noc => local_vc_write_tx_sig2,
|
||||
local_incr_tx_vec_noc => local_incr_tx_vec_sig2
|
||||
|
||||
);
|
||||
|
||||
full_noc_inst1 : full_noc
|
||||
|
|
@ -203,56 +186,113 @@ begin
|
|||
--rx
|
||||
local_rx_sig(1) <= local_tx_sig1;
|
||||
local_vc_write_rx_sig(4) <= local_vc_write_tx_sig1;
|
||||
local_incr_rx_vec_sig(0) <= local_incr_tx_vec_sig2;--- sig1
|
||||
--tx
|
||||
local_rx_sig1 <= local_tx_sig(1);
|
||||
local_vc_write_rx_sig1 <= local_vc_write_tx_sig(4);
|
||||
local_incr_rx_vec_sig1 <= local_incr_tx_vec_sig(4);
|
||||
|
||||
--inst2 [rx_dma <= tx_noc] & [rx_noc <= tx_dma] source zero[0]
|
||||
-- rx
|
||||
local_rx_sig(0) <= local_tx_sig2;
|
||||
local_vc_write_rx_sig(0) <= local_vc_write_tx_sig2;
|
||||
local_incr_rx_vec_sig(4) <= local_incr_tx_vec_sig1;--- sig2
|
||||
--tx destination one[1]
|
||||
local_rx_sig2 <= local_tx_sig(0);
|
||||
local_vc_write_rx_sig2 <= local_vc_write_tx_sig(0);
|
||||
local_incr_rx_vec_sig2 <= local_incr_tx_vec_sig(0);
|
||||
|
||||
|
||||
-- Simulation process to assign values to CtrlCommand
|
||||
simproc: process
|
||||
begin
|
||||
-- local_vc_write_tx_noc2 <= '0';
|
||||
cmd_valid <= '0';
|
||||
rst_tb <= '0';
|
||||
wait for 10 ns;
|
||||
rst_tb <= '1';
|
||||
wait for 40 ns;
|
||||
-----------------------------------------------Test1---------------------------------------------------
|
||||
|
||||
|
||||
|
||||
cmd_inst_funct2 <= "0011110"; --#define DMA_WRITE_TO_RAM 30 /// 0X1E
|
||||
cmd_inst_funct1 <= "0011111"; --#define DMA_READ_FROM_RAM 31 /// 0X1F
|
||||
|
||||
cmd_rs1_1 <= std_logic_vector(to_unsigned(0, 57)) & "0000010"; --7 bit address & 57 bit zeros
|
||||
cmd_rs1_2 <= std_logic_vector(to_unsigned(0, 57)) & "0001000"; --7 bit address & 57 bit zeros
|
||||
|
||||
cmd_rs2_1 <= std_logic_vector(to_unsigned(0, 59)) & "00100"; --5 bit size & 59 bit zeros
|
||||
cmd_rs2_2 <= std_logic_vector(to_unsigned(0, 59)) & "00100"; --5 bit size & 59 bit zeros
|
||||
cmd_rs2_1 <= std_logic_vector(to_unsigned(0, 59)) & "11100"; --5 bit size & 59 bit zeros
|
||||
cmd_rs2_2 <= std_logic_vector(to_unsigned(0, 59)) & "11100"; --5 bit size & 59 bit zeros
|
||||
|
||||
wait for 20 ns;
|
||||
cmd_valid <= '1';
|
||||
wait for 40 ns;
|
||||
cmd_valid <= '0';
|
||||
-- local_vc_write_tx_noc2 <= '1';
|
||||
wait for 180 ns;
|
||||
-- local_vc_write_tx_noc2 <= '0';
|
||||
|
||||
for i in 0 to to_integer(unsigned(cmd_rs2_1)) loop
|
||||
if(ram_sig1(to_integer(unsigned(cmd_rs1_1)) + i ) /= ram_sig2(to_integer(unsigned(cmd_rs1_2)) + i)) then
|
||||
report "Test is failed: memory elements are not equal at location " &
|
||||
report "Test1 is failed: memory elements are not equal at location " &
|
||||
"cmd_rs1_1 = " & integer'image(to_integer(unsigned(cmd_rs1_1)+i)) &
|
||||
", cmd_rs1_2 = " & integer'image(to_integer(unsigned(cmd_rs1_2)+i))
|
||||
severity note;
|
||||
failed_status_test1 <= '1';
|
||||
exit; -- Exit the loop
|
||||
stop;--exit; -- Exit the loop
|
||||
end if;
|
||||
end loop;
|
||||
|
||||
wait for 200 ns;--200
|
||||
----------------------------------------------Test2------------------------------------------------------
|
||||
cmd_inst_funct1 <= "0011110"; --#define DMA_WRITE_TO_RAM 30 /// 0X1E
|
||||
cmd_inst_funct2 <= "0011111"; --#define DMA_READ_FROM_RAM 31 /// 0X1F
|
||||
|
||||
cmd_rs1_2 <= std_logic_vector(to_unsigned(0, 57)) & "0000101"; --7 bit address & 57 bit zeros
|
||||
cmd_rs1_1 <= std_logic_vector(to_unsigned(0, 57)) & "0001101"; --7 bit address & 57 bit zeros
|
||||
|
||||
cmd_rs2_2 <= std_logic_vector(to_unsigned(0, 59)) & "00100"; --5 bit size & 59 bit zeros
|
||||
cmd_rs2_1 <= std_logic_vector(to_unsigned(0, 59)) & "00100"; --5 bit size & 59 bit zeros
|
||||
|
||||
wait for 20 ns;
|
||||
cmd_valid <= '1';
|
||||
wait for 40 ns;
|
||||
cmd_valid <= '0';
|
||||
wait for 180 ns;
|
||||
|
||||
for i in 0 to to_integer(unsigned(cmd_rs2_1)) loop
|
||||
if(ram_sig1(to_integer(unsigned(cmd_rs1_1)) + i ) /= ram_sig2(to_integer(unsigned(cmd_rs1_2)) + i)) then
|
||||
report "Test2 is failed: memory elements are not equal at location " &
|
||||
"cmd_rs1_1 = " & integer'image(to_integer(unsigned(cmd_rs1_1)+i)) &
|
||||
", cmd_rs1_2 = " & integer'image(to_integer(unsigned(cmd_rs1_2)+i))
|
||||
severity note;
|
||||
failed_status_test1 <= '1';
|
||||
stop;--exit; -- Exit the loop
|
||||
end if;
|
||||
end loop;
|
||||
|
||||
wait for 100 ns;
|
||||
|
||||
----------------------------------------------Test3------------------------------------------------------
|
||||
cmd_inst_funct1 <= "0011110"; --#define DMA_WRITE_TO_RAM 30 /// 0X1E
|
||||
cmd_inst_funct2 <= "0011111"; --#define DMA_READ_FROM_RAM 31 /// 0X1F
|
||||
|
||||
cmd_rs1_2 <= std_logic_vector(to_unsigned(0, 57)) & "0001101"; --7 bit address & 57 bit zeros
|
||||
cmd_rs1_1 <= std_logic_vector(to_unsigned(0, 57)) & "0010101"; --7 bit address & 57 bit zeros
|
||||
|
||||
cmd_rs2_2 <= std_logic_vector(to_unsigned(0, 59)) & "01100"; --5 bit size & 59 bit zeros
|
||||
cmd_rs2_1 <= std_logic_vector(to_unsigned(0, 59)) & "01100"; --5 bit size & 59 bit zeros
|
||||
|
||||
wait for 20 ns;
|
||||
cmd_valid <= '1';
|
||||
wait for 40 ns;
|
||||
cmd_valid <= '0';
|
||||
wait for 180 ns;
|
||||
|
||||
for i in 0 to to_integer(unsigned(cmd_rs2_1)) loop
|
||||
if(ram_sig1(to_integer(unsigned(cmd_rs1_1)) + i ) /= ram_sig2(to_integer(unsigned(cmd_rs1_2)) + i)) then
|
||||
report "Test3 is failed: memory elements are not equal at location " &
|
||||
"cmd_rs1_1 = " & integer'image(to_integer(unsigned(cmd_rs1_1)+i)) &
|
||||
", cmd_rs1_2 = " & integer'image(to_integer(unsigned(cmd_rs1_2)+i))
|
||||
severity note;
|
||||
failed_status_test1 <= '1';
|
||||
stop;--exit; -- Exit the loop
|
||||
end if;
|
||||
end loop;
|
||||
|
||||
|
|
@ -260,14 +300,11 @@ begin
|
|||
|
||||
--------------------------------------------------------------------------------------------------------------
|
||||
if failed_status_test1 = '0' then
|
||||
report "Test is passed: memory elements are equal starting locations " &
|
||||
report "All Test's are passed: memory elements are equal starting locations " &
|
||||
"cmd_rs1_1 = " & integer'image(to_integer(unsigned(cmd_rs1_1))) &
|
||||
", cmd_rs1_2 = " & integer'image(to_integer(unsigned(cmd_rs1_2)))
|
||||
severity note;
|
||||
end if;
|
||||
wait for 1000 ns;
|
||||
|
||||
|
||||
-- -- wait for 1000 ns ;
|
||||
end process;
|
||||
end architecture;
|
||||
|
|
|
|||
|
|
@ -11,10 +11,6 @@ use ieee.numeric_std.all;
|
|||
|
||||
----------------------NoC Interface Entity---------------------------
|
||||
entity noc_interface is
|
||||
-- constant DATA_SIZE : integer := 7; -- Define constant for vector size for data of 8 bits
|
||||
-- constant LENGTH : integer := 4; -- Define constant for vector size for size of Id's 5 bits
|
||||
-- constant PACKET : integer := 11; -- Define constant for vector size for size of Id's 12 bits
|
||||
-- constant REG_SIZE : integer := 31; -- Define constant for vector size for size of Reg 31 bits
|
||||
generic (
|
||||
DATA_SIZE : natural := 7; -- Define constant for vector size for data of 8 bits
|
||||
LENGTH : natural := 4; -- Define constant for vector size for size of Id's 5 bits
|
||||
|
|
@ -49,10 +45,6 @@ architecture noc_interface_arch of noc_interface is
|
|||
signal count : std_logic_vector(LENGTH downto 0);
|
||||
signal sent_packet : std_logic_vector(LENGTH downto 0);
|
||||
signal packet_len : std_logic_vector(LENGTH downto 0);
|
||||
|
||||
|
||||
--signal packet_length : std_logic_vector(4 downto 0);
|
||||
|
||||
begin
|
||||
rxprocess : process(clk, rst)
|
||||
begin
|
||||
|
|
@ -60,7 +52,7 @@ begin
|
|||
rx_packet_length_noc <= (others => '0');
|
||||
local_noc_tx <= (others => '0');
|
||||
local_vc_write_tx_noc <= '0';
|
||||
--local_incr_tx_vec_noc <= '0';
|
||||
local_incr_tx_vec_noc <= '0';-----
|
||||
receive_valid_to_dma <= '0';
|
||||
sent_ack_to_dma <= (others => '0');
|
||||
data_bus_noc_out <= (others => '0');
|
||||
|
|
@ -80,25 +72,28 @@ begin
|
|||
count <= (others => '0'); --counter reset
|
||||
packet_id <= local_noc_rx(28 downto 17); --current packetid
|
||||
receive_valid_to_dma <= '1';
|
||||
local_incr_tx_vec_noc <= '1';-------
|
||||
elsif(unsigned(count) <= unsigned(packet_len) and unsigned(packet_len) > 0) then
|
||||
report "receive_valid_to_dma is 1 from Line 80";
|
||||
|
||||
receive_valid_to_dma <= '1'; --valid to DMA
|
||||
count <= std_logic_vector(unsigned(count) + 1); --counter update
|
||||
data_bus_noc_out <= local_noc_rx(DATA_SIZE downto 0 ); --NoC is given to RAM
|
||||
local_incr_tx_vec_noc <= '1';-------
|
||||
else
|
||||
report "receive_valid_to_dma is 0 from Line 86";
|
||||
packet_len <= (others=>'0');
|
||||
receive_valid_to_dma <= '0';
|
||||
data_bus_noc_out <= (others=>'0');
|
||||
count <= (others=>'0');
|
||||
local_incr_tx_vec_noc <= '0';-------
|
||||
|
||||
end if;
|
||||
|
||||
--------------------Writing to NoC----------------------------------
|
||||
|
||||
elsif ((sent_valid_from_dma = '1') and (to_integer(unsigned(tx_packet_length_noc)) >= 0)) then -- the valid from dma is one cycle behind
|
||||
if(sent_packet = "00000") then
|
||||
--sent_ack_to_dma <= std_logic_vector(unsigned(sent_packet) + 1); --to DMA updated value
|
||||
sent_packet <= std_logic_vector(unsigned(sent_packet) + 1);
|
||||
--updating packet id
|
||||
local_noc_tx <= "100" & packet_id & SOURCE_ID & DEST_ID & tx_packet_length_noc;
|
||||
|
|
@ -113,7 +108,7 @@ begin
|
|||
rx_packet_length_noc <= (others => '0');
|
||||
local_noc_tx <= (others => '0');
|
||||
local_vc_write_tx_noc <= '0';
|
||||
---local_incr_tx_vec_noc <= '0';
|
||||
local_incr_tx_vec_noc <= '0';---
|
||||
receive_valid_to_dma <= '0';
|
||||
sent_ack_to_dma <= (others => '0');
|
||||
data_bus_noc_out <= (others => '0');
|
||||
|
|
|
|||
|
|
@ -11,40 +11,36 @@ use ieee.numeric_std.all;
|
|||
|
||||
----------------------RoCC Interface Entity---------------------------
|
||||
entity rocc_interface is
|
||||
-- constant INST_SIZE : integer := 6; -- Define constant for vector size for inst of 6 bits
|
||||
-- constant LENGTH : integer := 4; -- Define constant for vector size for size of Id's 5 bits
|
||||
-- constant PACKET : integer := 11; -- Define constant for vector size for size of Id's 12 bits
|
||||
-- constant REG_SIZE : integer := 63; -- Define constant for vector size for size of Reg 63 bits
|
||||
generic (
|
||||
DMA_WRITE_TO_RAM : std_logic_vector(6 downto 0) := "0001111";
|
||||
DMA_READ_TO_RAM : std_logic_vector(6 downto 0) := "1111111";
|
||||
CORE_WRITE_FUNC : natural := 30; -- Write function from the core
|
||||
CORE_READ_FUNC : natural := 31; -- Read function from the core
|
||||
INST_SIZE : natural := 6; -- Define constant for vector size for inst of 6 bits
|
||||
LENGTH : natural := 4; -- Define constant for vector size for size of Id's 5 bits
|
||||
PACKET : natural := 11; -- Define constant for vector size for size of Id's 12 bits
|
||||
REG_SIZE : natural := 63 -- Define constant for vector size for size of Reg 63 bits
|
||||
DMA_WRITE_TO_RAM : std_logic_vector(6 downto 0) := "0001111";
|
||||
DMA_READ_TO_RAM : std_logic_vector(6 downto 0) := "1111111";
|
||||
CORE_WRITE_FUNC : natural := 30; -- Write function from the core
|
||||
CORE_READ_FUNC : natural := 31; -- Read function from the core
|
||||
INST_SIZE : natural := 6; -- Define constant for vector size for inst of 6 bits
|
||||
LENGTH : natural := 4; -- Define constant for vector size for size of Id's 5 bits
|
||||
PACKET : natural := 11; -- Define constant for vector size for size of Id's 12 bits
|
||||
REG_SIZE : natural := 63 -- Define constant for vector size for size of Reg 63 bits
|
||||
);
|
||||
port(
|
||||
clk : in std_logic;
|
||||
rst : in std_logic;
|
||||
cmd_valid : in std_logic; --From Core
|
||||
cmd_inst_funct : in std_logic_vector(INST_SIZE downto 0); --From Core
|
||||
cmd_inst_opcode : in std_logic_vector(INST_SIZE downto 0); --From Core
|
||||
cmd_inst_rd : in std_logic_vector(LENGTH downto 0); --From Core
|
||||
cmd_inst_rs1 : in std_logic_vector(LENGTH downto 0); --From Core
|
||||
cmd_inst_rs2 : in std_logic_vector(LENGTH downto 0); --From Core
|
||||
cmd_inst_xd : in std_logic; --From Core
|
||||
cmd_inst_xs1 : in std_logic; --From Core
|
||||
cmd_inst_xs2 : in std_logic; --From Core
|
||||
cmd_rs1 : in std_logic_vector(REG_SIZE downto 0); --From Core
|
||||
cmd_rs2 : in std_logic_vector(REG_SIZE downto 0); --From Core
|
||||
data_trans_from_dma : in std_logic_vector(LENGTH downto 0); --From DMA
|
||||
cmd_busy : out std_logic; --To Core
|
||||
cmd_ready : out std_logic; --To Core --always one
|
||||
funct_to_dma : out std_logic_vector(INST_SIZE downto 0); --To DMA
|
||||
address_to_dma : out std_logic_vector(INST_SIZE downto 0); --To DMA
|
||||
size_to_dma : out std_logic_vector(LENGTH downto 0) --To DMA
|
||||
clk : in std_logic;
|
||||
rst : in std_logic;
|
||||
cmd_valid : in std_logic; --From Core
|
||||
cmd_inst_funct : in std_logic_vector(INST_SIZE downto 0); --From Core
|
||||
cmd_inst_opcode : in std_logic_vector(INST_SIZE downto 0); --From Core
|
||||
cmd_inst_rd : in std_logic_vector(LENGTH downto 0); --From Core
|
||||
cmd_inst_rs1 : in std_logic_vector(LENGTH downto 0); --From Core
|
||||
cmd_inst_rs2 : in std_logic_vector(LENGTH downto 0); --From Core
|
||||
cmd_inst_xd : in std_logic; --From Core
|
||||
cmd_inst_xs1 : in std_logic; --From Core
|
||||
cmd_inst_xs2 : in std_logic; --From Core
|
||||
cmd_rs1 : in std_logic_vector(REG_SIZE downto 0); --From Core
|
||||
cmd_rs2 : in std_logic_vector(REG_SIZE downto 0); --From Core
|
||||
data_trans_from_dma : in std_logic_vector(LENGTH downto 0); --From DMA
|
||||
cmd_busy : out std_logic; --To Core
|
||||
cmd_ready : out std_logic; --To Core --always one
|
||||
funct_to_dma : out std_logic_vector(INST_SIZE downto 0); --To DMA
|
||||
address_to_dma : out std_logic_vector(INST_SIZE downto 0); --To DMA
|
||||
size_to_dma : out std_logic_vector(LENGTH downto 0) --To DMA
|
||||
);
|
||||
end entity;
|
||||
|
||||
|
|
@ -55,8 +51,6 @@ architecture rocc_interface_arch of rocc_interface is
|
|||
signal cmd_rs2_sig : std_logic_vector(REG_SIZE downto 0);
|
||||
Signal cmd_inst_funct_sig : std_logic_vector(INST_SIZE downto 0);
|
||||
Signal cmd_valid_sig : std_logic;
|
||||
--signal Sent_packet : std_logic_vector(4 downto 0);
|
||||
--signal packet_length : std_logic_vector(4 downto 0);
|
||||
|
||||
begin
|
||||
process(clk, rst)
|
||||
|
|
@ -70,33 +64,38 @@ begin
|
|||
size_to_dma <= (others => '0');
|
||||
cmd_rs1_sig <= (others => '0');
|
||||
cmd_rs2_sig <= (others => '0');
|
||||
cmd_inst_funct_sig <= (others => '0');
|
||||
cmd_inst_funct_sig <= (others => '0');---
|
||||
|
||||
elsif rising_edge(clk) then
|
||||
|
||||
--------------------Send to the DMA--------------------------------
|
||||
|
||||
if((cmd_valid_sig = '1') and (cmd_rs2_sig(LENGTH downto 0) > data_trans_from_dma)) then
|
||||
if cmd_inst_funct = std_logic_vector(to_unsigned(CORE_WRITE_FUNC, 7)) then --#define DMA_WRITE_TO_RAM 30 /// 0X1E
|
||||
if((cmd_valid_sig = '1') and (to_integer(unsigned(cmd_rs2_sig(LENGTH downto 0))) > (to_integer(unsigned(data_trans_from_dma))+1))) then
|
||||
if cmd_inst_funct_sig = std_logic_vector(to_unsigned(CORE_WRITE_FUNC, 7)) then --#define DMA_WRITE_TO_RAM 30 /// 0X1E
|
||||
funct_to_dma <= DMA_WRITE_TO_RAM;
|
||||
elsif cmd_inst_funct = std_logic_vector(to_unsigned(CORE_READ_FUNC, 7))then--"001111" then --#define DMA_READ_FROM_RAM 31 /// 0X1F
|
||||
elsif cmd_inst_funct_sig = std_logic_vector(to_unsigned(CORE_READ_FUNC, 7))then--"001111" then --#define DMA_READ_FROM_RAM 31 /// 0X1F
|
||||
funct_to_dma <= DMA_READ_TO_RAM;
|
||||
else
|
||||
funct_to_dma <= (others => '0');
|
||||
end if;
|
||||
address_to_dma <= cmd_rs1_sig(INST_SIZE downto 0);
|
||||
size_to_dma <= cmd_rs2_sig(LENGTH downto 0);
|
||||
cmd_busy <= '1';
|
||||
--------------------Reading from RoCC--------------------------------
|
||||
|
||||
elsif (cmd_valid = '1') then
|
||||
elsif (cmd_valid = '1' and (to_integer(unsigned(data_trans_from_dma)) = 0)) then
|
||||
cmd_rs1_sig <= cmd_rs1;
|
||||
cmd_rs2_sig <= cmd_rs2; --size 4 downto 0 [5bits]
|
||||
cmd_inst_funct_sig <= cmd_inst_funct;
|
||||
cmd_inst_funct_sig <= cmd_inst_funct;----
|
||||
cmd_valid_sig <= '1';
|
||||
cmd_busy <= '1';
|
||||
|
||||
else
|
||||
cmd_valid_sig <= '0';
|
||||
cmd_busy <= '0';
|
||||
cmd_rs1_sig <= (others => '0');
|
||||
cmd_rs1_sig <= (others => '0');
|
||||
funct_to_dma <= (others => '0');
|
||||
cmd_inst_funct_sig <= (others => '0');
|
||||
|
||||
end if;
|
||||
|
|
|
|||
|
|
@ -2,14 +2,12 @@ library ieee;
|
|||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
----------------------ram Entity---------------------------
|
||||
----------------------------------------ram Entity---------------------------------------------------
|
||||
entity single_port_ram is
|
||||
generic (
|
||||
DATA_SIZE : natural := 7; -- Default source ID should be changed
|
||||
ADDRESS_SIZE : natural := 6 -- Default destination ID should be changed
|
||||
);
|
||||
--constant DATA_SIZE : integer := 7; -- Define constant for vector size for data of 8 bits
|
||||
--constant ADDRESS_SIZE : integer := 6; -- Define constant for vector size for address 7 bits
|
||||
port(
|
||||
clk : in std_logic;
|
||||
rst : in std_logic;
|
||||
|
|
@ -21,15 +19,13 @@ entity single_port_ram is
|
|||
);
|
||||
end entity;
|
||||
|
||||
----------------------ram Behaviour------------------------
|
||||
----------------------------------------ram Behaviour--------------------------------------------------
|
||||
architecture single_port_ram_behav of single_port_ram is
|
||||
|
||||
------- define the new type for the 128x8 ram
|
||||
type ram_array is array (0 to 127 ) of std_logic_vector (DATA_SIZE downto 0);
|
||||
-------- initial values in the ram to X00
|
||||
signal ram: ram_array := (others=>x"00");
|
||||
signal initialized : std_logic; -- Initialization flag
|
||||
|
||||
begin
|
||||
process(clk, rst)
|
||||
begin
|
||||
|
|
@ -46,7 +42,7 @@ begin
|
|||
initialized <= '0';
|
||||
end if;
|
||||
-- synthesis translate_on
|
||||
--Read Write functionality of ram
|
||||
|
||||
if (read_enable = '1' and write_enable = '0' )then --read enable; [MSB] READ Enable [LSB] WRITE Enable
|
||||
data_bus_out <= ram(to_integer(unsigned(address_bus(ADDRESS_SIZE downto 0 )))); -- read data from ram
|
||||
elsif (read_enable = '0' and write_enable = '1') then --write enable; [MSB] READ Enable [LSB] WRITE Enable
|
||||
|
|
|
|||
Loading…
Reference in a new issue