kkoloth
91dbf4503c
Implementation of the DMA logic up to 2/12/24. [Note: Testbench creation and full_DMA signal mapping is pending]
217 lines
No EOL
12 KiB
VHDL
217 lines
No EOL
12 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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----------------------Full DMA Entity---------------------------
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entity Full_DMA is
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generic (
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SOURCE_ID_NEW : std_logic_vector(5 downto 0) := "000000"; -- Default source ID should be changed
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DEST_ID_NEW : std_logic_vector(5 downto 0) := "000001" -- Default destination ID should be changed
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);
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port(
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clk : in std_logic;
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rst : in std_logic;
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local_noc_rx : in std_logic_vector(31 downto 0);--- --From Noc
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local_vc_write_tx_noc : in std_logic; ---_vector(192-1 downto 0);--From NoC
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cmd_valid : in std_logic; --From Core
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Cmd_inst_funct : in std_logic_vector(6 downto 0); --From Core
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Cmd_inst_opcode : in std_logic_vector(6 downto 0); --From Core
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Cmd_inst_rd : in std_logic_vector(4 downto 0); --From Core
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Cmd_inst_rs1 : in std_logic_vector(4 downto 0); --From Core
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Cmd_inst_rs2 : in std_logic_vector(4 downto 0); --From Core
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Cmd_inst_xd : in std_logic; --From Core
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Cmd_inst_xs1 : in std_logic; --From Core
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Cmd_inst_xs2 : in std_logic; --From Core
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Cmd_rs1 : in std_logic_vector(63 downto 0); --From Core
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Cmd_rs2 : in std_logic_vector(63 downto 0); --From Core
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Cmd_busy : out std_logic; --To Core
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Cmd_ready : out std_logic; --To Core --always one
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local_noc_tx : out std_logic_vector(31 downto 0);--- --To NoC
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local_vc_write_rx_noc : out std_logic ---_vector(192-1 downto 0);--To NoC
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);
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end entity;
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----------------------Full DMA Behaviour------------------------
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architecture Full_DMA_Arch of Full_DMA is
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component Single_Port_RAM is
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port(
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clk : in std_logic;
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rst : in std_logic;
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Address_bus : in std_logic_vector(7 downto 0); --From DMA
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Read_write_Enable : in std_logic_vector(1 downto 0); --From DMA
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Data_bus_in : in std_logic_vector(7 downto 0); --From Noc
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Data_bus_out : out std_logic_vector(7 downto 0) --From Noc
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);
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end component;
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component Noc_Interface is
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generic (
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SOURCE_ID : std_logic_vector(5 downto 0) := "000000"; -- Default source ID should be changed
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DEST_ID : std_logic_vector(5 downto 0) := "000001" -- Default destination ID should be changed
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);
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port(
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clk : in std_logic;
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rst : in std_logic;
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Sent_valid_from_DMA : in std_logic; --From DMA
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Data_bus_noc_in : in std_logic_vector(7 downto 0); --From RAM
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tx_packet_length_noc : in std_logic_vector(4 downto 0); --From DMA
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local_noc_rx : in std_logic_vector(31 downto 0);--- --From Noc
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local_vc_write_tx_noc: in std_logic; ---_vector(192-1 downto 0);--From NoC
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rx_packet_length_noc : out std_logic_vector(4 downto 0); --To DMA
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local_noc_tx : out std_logic_vector(31 downto 0);--- --To NoC
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local_vc_write_rx_noc: out std_logic; ---_vector(192-1 downto 0);--To NoC
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Receive_valid_to_DMA : out std_logic; --To DMA
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Sent_Ack_to_DMA : out std_logic_vector(4 downto 0);-----------To DMA
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Data_bus_noc_out : out std_logic_vector(7 downto 0) --To RAM
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);
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end component;
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component RoCC_Interface is
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port(
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clk : in std_logic;
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rst : in std_logic;
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cmd_valid : in std_logic; --From Core
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Cmd_inst_funct : in std_logic_vector(6 downto 0); --From Core
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Cmd_inst_opcode : in std_logic_vector(6 downto 0); --From Core
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Cmd_inst_rd : in std_logic_vector(4 downto 0); --From Core
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Cmd_inst_rs1 : in std_logic_vector(4 downto 0); --From Core
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Cmd_inst_rs2 : in std_logic_vector(4 downto 0); --From Core
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Cmd_inst_xd : in std_logic; --From Core
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Cmd_inst_xs1 : in std_logic; --From Core
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Cmd_inst_xs2 : in std_logic; --From Core
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Cmd_rs1 : in std_logic_vector(63 downto 0); --From Core
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Cmd_rs2 : in std_logic_vector(63 downto 0); --From Core
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Data_trans_from_DMA : in std_logic_vector(4 downto 0); --From DMA
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Cmd_busy : out std_logic; --To Core
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Cmd_ready : out std_logic; --To Core --always one
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Funct_to_DMA : out std_logic_vector(6 downto 0); --To DMA
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Address_to_DMA : out std_logic_vector(6 downto 0); --To DMA
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Size_to_DMA : out std_logic_vector(4 downto 0) --To DMA
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);
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end component;
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component DMA_Controller is
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port(
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clk : in std_logic;
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rst : in std_logic;
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rx_packet_length_noc_to_DMA : in std_logic_vector(4 downto 0); --To DMA From Noc
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Receive_valid_to_DMA_from_Noc : in std_logic; --To DMA From Noc
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Sent_Ack_to_DMA_from_Noc : in std_logic_vector(4 downto 0);--------To DMA From Noc
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Funct_core_to_DMA : in std_logic_vector(6 downto 0); --To DMA From Core
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Address_core_to_DMA : in std_logic_vector(6 downto 0); --To DMA From Core
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Size_core_to_DMA : in std_logic_vector(4 downto 0); --To DMA From Core
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Address_bus_From_DMA : out std_logic_vector(7 downto 0); --From DMA To RAM
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Read_write_Enable_From_DMA : out std_logic_vector(1 downto 0); --From DMA To RAM
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Sent_valid_from_DMA_to_NoC : out std_logic; --From DMA To NoC
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tx_packet_length_noc_From_DMA : out std_logic_vector(4 downto 0); --From DMA To NoC
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Data_trans_from_DMA_to_core : out std_logic_vector(4 downto 0) --From DMA To Core
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);
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end component;
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signal Address_bus_sig : std_logic_vector(7 downto 0);
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signal Read_write_Enable_sig : std_logic_vector(1 downto 0);
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signal Data_bus_in_sig : std_logic_vector(7 downto 0);
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signal Data_bus_out_sig : std_logic_vector(7 downto 0);
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signal Sent_valid_from_DMA_sig : std_logic;
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signal Data_bus_noc_in_sig : std_logic_vector(7 downto 0);
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signal tx_packet_length_noc_sig : std_logic_vector(4 downto 0);
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signal rx_packet_length_noc_sig : std_logic_vector(4 downto 0);
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signal local_noc_tx_sig : std_logic_vector(31 downto 0);
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signal local_vc_write_rx_noc_sig : std_logic;
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signal Receive_valid_to_DMA_sig : std_logic;
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signal Sent_Ack_to_DMA_sig : std_logic_vector(4 downto 0);
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signal Data_bus_noc_out_sig : std_logic_vector(7 downto 0);
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signal Data_trans_from_DMA_sig : std_logic_vector(4 downto 0);
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signal Funct_to_DMA_sig : std_logic_vector(6 downto 0);
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signal Address_to_DMA_sig : std_logic_vector(6 downto 0);
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signal Size_to_DMA_sig : std_logic_vector(4 downto 0);
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signal rx_packet_length_noc_to_DMA_sig : std_logic_vector(4 downto 0);
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signal Receive_valid_to_DMA_from_Noc_sig : std_logic;
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signal Sent_Ack_to_DMA_from_Noc_sig : std_logic_vector(4 downto 0);
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signal Funct_core_to_DMA_sig : std_logic_vector(6 downto 0);
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signal Address_core_to_DMA_sig : std_logic_vector(6 downto 0);
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Signal Size_core_to_DMA_sig : std_logic_vector(4 downto 0);
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signal Address_bus_From_DMA_sig : std_logic_vector(7 downto 0);
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signal Read_write_Enable_From_DMA_sig : std_logic_vector(1 downto 0);
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signal Sent_valid_from_DMA_to_NoC_sig : std_logic;
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signal tx_packet_length_noc_From_DMA_sig : std_logic_vector(4 downto 0);
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signal Data_trans_from_DMA_to_core_sig : std_logic_vector(4 downto 0);
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begin
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-- Single_Port_RAM mapping
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Single_Port_RAM_inst : Single_Port_RAM
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port map(
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clk => clk,
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rst => rst,
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Address_bus => Address_bus_sig,
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Read_write_Enable => Read_write_Enable_sig,
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Data_bus_in => Data_bus_in_sig, -- Assuming data input comes from NoC
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Data_bus_out => Data_bus_out_sig
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);
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-- Noc_Interface mapping
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Noc_Interface_inst : Noc_Interface
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generic map (
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SOURCE_ID => SOURCE_ID_NEW,
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DEST_ID => DEST_ID_NEW
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)
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port map(
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clk => clk,
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rst => rst,
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Sent_valid_from_DMA => Sent_valid_from_DMA_sig,
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Data_bus_noc_in => Data_bus_in_sig,
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tx_packet_length_noc => tx_packet_length_noc_sig,
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local_noc_rx => local_noc_rx, ---
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local_vc_write_tx_noc=> local_vc_write_tx_noc, ---
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rx_packet_length_noc => rx_packet_length_noc_sig,
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local_noc_tx => local_noc_tx, ---
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local_vc_write_rx_noc=> local_vc_write_rx_noc, ---
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Receive_valid_to_DMA => Receive_valid_to_DMA_sig,
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Sent_Ack_to_DMA => Sent_Ack_to_DMA_sig,
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Data_bus_noc_out => Data_bus_out_sig
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);
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-- RoCC_Interface mapping
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RoCC_Interface_inst : RoCC_Interface
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port map(
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clk => clk,
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rst => rst,
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cmd_valid => cmd_valid, ---
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Cmd_inst_funct => Cmd_inst_funct, ---
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Cmd_inst_opcode => Cmd_inst_opcode, ---
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Cmd_inst_rd => Cmd_inst_rd, ---
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Cmd_inst_rs1 => Cmd_inst_rs1, ---
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Cmd_inst_rs2 => Cmd_inst_rs2, ---
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Cmd_inst_xd => Cmd_inst_xd, ---
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Cmd_inst_xs1 => Cmd_inst_xs1, ---
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Cmd_inst_xs2 => Cmd_inst_xs2, ---
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Cmd_rs1 => Cmd_rs1, ---
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Cmd_rs2 => Cmd_rs2, ---
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Data_trans_from_DMA => Data_trans_from_DMA_sig,
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Cmd_busy => Cmd_busy, ---
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Cmd_ready => Cmd_ready, ---
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Funct_to_DMA => Funct_to_DMA_sig,
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Address_to_DMA => Address_to_DMA_sig,
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Size_to_DMA => Size_to_DMA_sig
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);
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-- DMA_Controller mapping
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DMA_Controller_inst : DMA_Controller
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port map(
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clk => clk,
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rst => rst,
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rx_packet_length_noc_to_DMA => rx_packet_length_noc_to_DMA_sig,
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Receive_valid_to_DMA_from_Noc => Receive_valid_to_DMA_from_Noc_sig,
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Sent_Ack_to_DMA_from_Noc => Sent_Ack_to_DMA_from_Noc_sig,
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Funct_core_to_DMA => Funct_core_to_DMA_sig,
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Address_core_to_DMA => Address_core_to_DMA_sig,
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Size_core_to_DMA => Size_core_to_DMA_sig,
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Address_bus_From_DMA => Address_bus_From_DMA_sig,
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Read_write_Enable_From_DMA => Read_write_Enable_From_DMA_sig,
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Sent_valid_from_DMA_to_NoC => Sent_valid_from_DMA_to_NoC_sig,
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tx_packet_length_noc_From_DMA => tx_packet_length_noc_From_DMA_sig,
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Data_trans_from_DMA_to_core => Data_trans_from_DMA_to_core_sig
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);
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----mapping need to be done yet------------- |