DMA_for_RoCC/DMA_CONTROLLER.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

----------------------DMA Controller Entity---------------------------
entity dma_controller is
    -- constant DATA_SIZE    : integer := 7; -- Define constant for vector size for data of 8 bits
    -- constant ADDRESS_SIZE : integer := 6; -- Define constant for vector size for address 7 bits  
    -- constant ID_SIZE      : integer := 4; -- Define constant for vector size for size of Id's 5 bits  
    generic (
        RAM_WRITE_CMD                 : natural := 15; -- Writing to ram command from rocc
        RAM_READ_CMD                  : natural := 127; -- Reading from ram command from rocc
        DATA_SIZE                     : natural := 7;  -- Define constant for vector size for data of 8 bits
        ADDRESS_SIZE                  : natural := 6;  -- Define constant for vector size for address 7 bits  
        ID_SIZE                       : natural := 4   -- Define constant for vector size for size of Id's 5 bits  
    ); 
    port(
        clk                           : in  std_logic; 
        rst                           : in  std_logic;       
        rx_packet_length_noc_to_dma   : in  std_logic_vector(ID_SIZE      downto 0);  --To DMA From Noc
        receive_valid_to_dma_from_noc : in  std_logic;                                --To DMA From Noc 
        sent_ack_to_dma_from_noc      : in  std_logic_vector(ID_SIZE      downto 0);--------To DMA From Noc
        funct_core_to_dma             : in  std_logic_vector(ADDRESS_SIZE downto 0);  --To DMA From Core 
        address_core_to_dma           : in  std_logic_vector(ADDRESS_SIZE downto 0);  --To DMA From Core 
        size_core_to_dma              : in  std_logic_vector(ID_SIZE      downto 0);  --To DMA From Core
        address_bus_from_dma          : out std_logic_vector(ADDRESS_SIZE    downto 0);  --From DMA To RAM
        read_enable_from_dma          : out std_logic;                                --From DMA To RAM
        write_enable_from_dma         : out std_logic;                                --From DMA To RAM
        sent_valid_from_dma_to_noc    : out std_logic;                                --From DMA To NoC     
        tx_packet_length_noc_from_dma : out std_logic_vector(ID_SIZE      downto 0);  --From DMA To NoC
        data_trans_from_dma_to_core   : out std_logic_vector(ID_SIZE      downto 0)   --From DMA To Core
        );
end entity;

----------------------DMA Controller Behaviour------------------------

architecture dma_controller_arch of dma_controller is
    --Signal count_from_noc            : std_logic_vector(ID_SIZE downto 0);
    Signal count_to_noc              : std_logic_vector(ID_SIZE downto 0);
    Signal address_to_ram            : std_logic_vector(ADDRESS_SIZE downto 0);


begin
    process(clk, rst)
    begin
        if rst = '0' then
            sent_valid_from_dma_to_noc    <= '0';
            read_enable_from_dma          <= '0';
            write_enable_from_dma         <= '0';
            address_bus_from_dma          <= (others => '0');        
            tx_packet_length_noc_from_dma <= (others => '0');
            data_trans_from_dma_to_core   <= (others => '0');
--            count_from_noc                <= (others => '0');
            count_to_noc                  <= (others => '0');
            address_to_ram                <= (others => '0');

           
        elsif rising_edge(clk) then
----------------------Writing to RAM from NOC------------------------

            if funct_core_to_dma = std_logic_vector(to_unsigned(RAM_WRITE_CMD, DATA_SIZE)) then             --- x"0f" 15 Its arbitarly choosen from RoCC_Interface 
                if unsigned(count_to_noc) < (unsigned(size_core_to_dma)) then --+10 will reproduce same valid signal comparing rx_packet_length_noc_to_dma = size_core_to_dma 
                    if count_to_noc  = "00000" then ---count_from_noc but not working in the wave simulation
                        address_to_ram         <= address_core_to_dma;
                        count_to_noc           <= std_logic_vector(unsigned(count_to_noc) + 1);
                        --write_enable_from_dma       <= '1';             --Write Enable
                    --end if;
                    elsif receive_valid_to_dma_from_noc = '1' then
                        address_bus_from_dma        <= address_to_ram;
                        --report "write_enable_from_dma is 1 from Line 68";
                        write_enable_from_dma       <= '1';             --Write Enable ----<<<<Why the value is not updateded>>>>
                        read_enable_from_dma        <= '0'; --'0'
                        data_trans_from_dma_to_core <= count_to_noc ;--  std_logic_vector(unsigned(count_to_noc) - 1)
                        address_to_ram              <= std_logic_vector(unsigned(address_to_ram) + 1);
                        count_to_noc                <= std_logic_vector(unsigned(count_to_noc) + 1);
                    else 
                        ----report "write_enable_from_dma is 0 from Line 75";
                        write_enable_from_dma       <= '0';             --Write Enable ----<<<<Why the value is not updateded>>>>
                        read_enable_from_dma        <= '0'; --'0'
                    end if;
            
                else 
                    ----report "write_enable_from_dma is 0 from Line 75";
                    write_enable_from_dma       <= '0';             --Write Enable ----<<<<Why the value is not updateded>>>>
                    read_enable_from_dma        <= '0'; --'0'
                end if;
            -- else
            --     count_from_noc                     <= (others => '0');
            --     read_enable_from_dma               <= '0';
            --     write_enable_from_dma              <= 'Z';--'0';     
            --     sent_valid_from_dma_to_noc         <= '0';
            -- end if;

----------------------Reading from RAM to NOC------------------------
            elsif funct_core_to_dma = std_logic_vector(to_unsigned(RAM_READ_CMD, DATA_SIZE)) then           ---  x"7f" 127 Its arbitarly choosen from RoCC_Interface  
                if unsigned(count_to_noc) < unsigned(size_core_to_dma) then --sent_ack_to_dma_from_noc could be used instead of the count to Noc
                    if count_to_noc  = "00000" then
                        address_to_ram                <= address_core_to_dma;
                        tx_packet_length_noc_from_dma <= size_core_to_dma; --giving the size to the header of the NoC flit
                        count_to_noc                <= std_logic_vector(unsigned(count_to_noc) + 1);
                        ---sent_valid_from_dma_to_noc  <= '1';
                    else
                        address_bus_from_dma        <= address_to_ram;
                        write_enable_from_dma       <= '0';             
                        read_enable_from_dma        <= '1';              --Read Enable
                        data_trans_from_dma_to_core <= sent_ack_to_dma_from_noc;
                        address_to_ram              <= std_logic_vector(unsigned(address_to_ram) + 1);
                        count_to_noc                <= std_logic_vector(unsigned(count_to_noc) + 1);
                        sent_valid_from_dma_to_noc  <= '1';
                    end if;
                elsif unsigned(count_to_noc) < (unsigned(size_core_to_dma)+2) then
                    count_to_noc                <= std_logic_vector(unsigned(count_to_noc) + 1);
                    sent_valid_from_dma_to_noc  <= '1';
                else
                    read_enable_from_dma                <= '0';
                    write_enable_from_dma               <= '0';
                    sent_valid_from_dma_to_noc          <= '0';      
                end if;
            else
                count_to_noc                        <= (others => '0');
                read_enable_from_dma                <= '0';
                --report "write_enable_from_dma is 0 from Line 111";
                write_enable_from_dma               <= '0';
                sent_valid_from_dma_to_noc          <= '0';      
            end if;
        end if;
    end process;
end architecture;